AMD EPYC 9006 Results Are Here and AMD Delivers a Knockout Part Deux

AMD EPYC 9996 Power and Efficiency

Performance is only half of it. We logged power during these runs, so here is what each chip used to do the work. The big catch is that these are the sensors each platform exposes, not wall meters, and the sensors do not all measure the same thing.

Here is the range each chip covered across these workloads.

The EPYC 9996 peaked at 613 W on the socket sensor and idled at 168 W, the highest idle here. AMD’s sensor has no DRAM rail, so the EPYC numbers leave out memory power that the Vera and Xeon numbers include. Maybe the big takeaway is just that we are now in the era of 600W TDP CPUs.

Key Lessons Learned

At some point, we have to put pencils down, but work will continue since we have more configurations to run through. The freight carrier’s 2-week delay put us behind. Here is where I am at with what we are presenting here, plus a bit more that we have done but was not ready for this piece.

AMD Venice to Turin

I am starting with the easy one. The SP7 platform is blazing fast with 16x DDR5 channels and PCIe Gen6, plus higher core counts. There is not really a clear overlap between generations. There is a big part of the hyper-scale market that just wants the most vCPUs per socket, and adding 33% more is the easy choice.

That same hyper-scale market can leverage new CXL 3.x controllers and reclaim DDR4 from fleets to lower memory costs. A decade (plus) ago, a new server CPU launch often had a lot of overlap between generational SKU stacks. Now, Venice is just a big upgrade across the board. There may be some cases where you would want Turin instead of Venice, but it feels like those will become corner cases in short order. Maybe the real one is just the availability.

AMD EPYC Venice vs NVIDIA Vera

NVIDIA is going to sell a ton of Vera CPUs. Vera Rubin GPU servers will use Vera CPUs, and demand is high. In single-core workloads, the Vera CPU did really well. NVIDIA had the insight that it was creating a high-performance core when it set out to design its Olympus cores, when many Arm-based server vendors were trying to design low-power and lower-performance cores.

Perhaps my bigger question is: where do these compete? If you want to run lots of always-on agents and need a lot of cores, you would buy Venice over Vera because of the thread-count difference. If you are building out an AMD Helios rack-scale GPU compute cluster, you are unlikely to put NVIDIA Vera as the host CPU. Likewise, if you are building NVIDIA rack-scale, you are unlikely to use Venice. If you need a lower-core-count part with only 8-16 cores and PCIe Gen6 I/O, AMD has something NVIDIA does not. If you want x86 so that existing software just works, then you will go with AMD.

It feels like agentic AI sockets aim to offer more than a set number of vCPUs per user at low cost and instead prioritize performance per core. That seems to be the battleground. As for which is faster, stay tuned as we go deeper into this comparison.

AMD EPYC Venice vs Intel Xeon

Intel’s CEO said that Diamond Rapids was not competitive in 2025. That led Intel to cut the 8-channel Diamond Rapids last year, which it confirmed to STH first.

In the 8-channel market, Intel does not have a PCIe Gen6 answer right now. In the 16-channel market, AMD is out first. That means that AMD will benefit from an EPYC 7002 “Rome” like cycle since other vendors (e.g. storage vendors) will have to validate their platforms first on Venice, seeing as how Diamond Rapids is behind in bringing Intel to the PCIe Gen6 market.

With that said, server CPU supply is tight enough that even with a clearly aging product that is now 2+ years old, Intel will sell a ton of Xeon 6 chips. There is a surprisingly large market now for server CPUs with PCIe Gen5 and supply.

At the same time, I find it hard to choose an Intel Xeon 6980P over an EPYC 9006 part when, in many cases, AMD is back to consolidating current-generation top-bin Intel CPUs on a 2:1 basis. This feels a lot like 2019 with Cascade Lake and Rome, with one key difference. AMD has gotten so large and is now six generations in, so it is a much more proven vendor than it was in the summer of 2019. In 2019, it was clear that Rome was far superior, but it was fighting a company with a much larger share. In 2026, Venice is similarly way ahead, but AMD’s share is very strong. It is just that in 2026 supply might matter as much, if not more than, the raw performance.

I feel very confident that AMD will sell a lot of Venice CPUs, but seemingly everyone that can make PCIe Gen5/ Gen6 CPUs will sell many of their CPUs too.

Final Words

Whether we looked at agentic AI workloads, traditional benchmarks, or hyper-scale style workloads, this is the most I have felt like AMD is going to market with something just better than what Intel has in a long time. Turin felt much closer, especially at the 128 P-core per socket level. Now AMD has a small socket line that Intel is not matching. There is an HPC part with a 10MB+ L3 cache per core in Venice-X. Verano is purpose-built for CPUs attached to GPUs. Then there is the consolidation and always-on agentic AI rack with up to 1024 threads in a single dual-socket server.

Venice is now the x86 CPU to get, and in many cases we do not need to qualify that with x86. More interestingly, while Zen 6 provides a significant uplift in performance from its microarchitectural improvements, it is not really an earth-shattering change. AMD is doing a lot of this work at the SoC and packaging level with smart application of its chip “glue”.

Given how good the part is, and just the crazy market for compute these days, I sense that Venice will do very well for AMD.