SPEC CPU2026
SPEC CPU2026 is the industry-standard CPU benchmark. Here we are showing rate results, which run many copies at once to measure throughput. These are our estimates and have not been submitted to SPEC. These runs use LLVM 22.1.4 with SMT on where the chip has it, and the charts show the copy count. Vendor submitted official results will be higher than ours, we are looking more at a least common denominator with the same LLVM tooling.

The EPYC 9996 scores 832.4 on one socket with 512 copies, some 71% higher than the EPYC 9965. Here, just having many cores helps, and a chunk of this performance uplift comes from having 33% more cores, as well as higher average clock speeds on those cores. Still, 71% is more than what the extra cores can deliver on their own, and the architecture higher IPC is doing a lot of the heavy lifting here. As a result, we get massive generational uplift with Venice.

Compared to Turin, the Venice chip’s performance uplift is even greater in floating point workloads, with an 81% improvement over AMD’s prior many-core monster. Otherwise, on a compettiive basis, the scores are closer in the floating poiint workloads, with Vera coming in second place despite having only about a third as many cores as the Venice part.
Core counts vary a lot here, so we also divided each score by the physical cores used.


This per-core metric really shows the difference in philosophy. I do not love the fact that we are comparing a 256-core Venice to the 88-core Vera because it gives Vera a lot more resources for each core. A better comparison is the EPYC 9686F, AMD’s high-frequnecy 96 core Venice part, but it is behind in the benchmarking sequence.

On integer, the EPYC 9996 beats Vera on all 14 benchmarks due to the sheer number of cores it has.

Floating point is where Vera gets close. It beats the EPYC 9996 on 2 of 12 benchmarks, 749.fotonik3d_r and 765.roms_r. Those look more like memory bandwidth tests than core tests, so it may be different with a higher-bandwidth EPYC setup.


