AMD EPYC 9006 Results Are Here and AMD Delivers a Knockout Part Deux

AMD Zen 6 Microarchitecture: AMD’s Greatest Gains Yet

With the release of a new generation of server CPUs from AMD comes a new microarchitecture backing them. AMD’s now battle-tested Zen microarchitecture is back for its 6^th round. And, in a launch that underscores just how much the CPU world has changed in just the last couple of years, AMD is launching its next-generation CPU architecture in servers first, rather than following up with server parts last.

This also means that we are getting our first in-depth look at a new AMD CPU microarchitecture through the lens of server needs rather than client needs. Zen 6 is, of course, designed to be a highly versatile architecture that will scale from laptops and embedded up to AMD’s flagship server chips. But it none the less colors things a bit differently than we have seen for any of AMD’s past Zen microarchitecture launches over the past decade.

So what is new for Zen 6? Back in 2024 with the launch of the Zen 5 microarchitecture, AMD’s Corporate Fellow and lead Zen architect Mike Clark said that the then-new microarchitecture would be a foundation for multiple generations of Zen to come. And, true to his word, that is an apt description for the Zen 6 microarchitecture. There are not any massive, paradigm-shifting changes to the microarchitecture relative to Zen 5. But there are a number of tune-ups across the board to improve the performance of the chip and to make the best use possible of TSMC’s 2nm process node.

Zen 6 IPC: +20% In Enterprise and Cloud Server Workloads

Let us start with a high-level look at the Zen 6 microarchitecture. As with the past couple of generations of the Zen microarchitecture, AMD is producing both a large version of the CPU core as well as a compact version for high density configurations. Both of these variations will, once again, be architecturally identical: every feature, every data path between the two is the same. Which means that at the level of talking about a single CPU core, the two designs are identical from a microarchitectural perspective.

For the Zen 6 microarchitecture, AMD is touting a 20% improvement in IPC versus the Zen 5 microarchitecture.

Making apples-to-apples comparisons is a bit tricky here since IPC gains can vary wildly from workload to workload, and the workloads evolve over time. But the closest analog in prior generations was AMD’s claims for the Zen 5 Turin launch, when the company said that Zen 5 offered a 17% IPC improvement over Zen 4. In other words, the IPC uplift over Zen 5 is slated to be even greater than it was for Zen 5 over Zen 4, and for that matter Zen 4 over Zen 3.

Depending on the specific workload and how things shake out, a 20% IPC uplift in enterprise workloads would represent one of AMD’s most impactful Zen microarchitecture improvements since the microarchitecture launched, rivaling (if not slightly exceeding) the improvements brought by the Zen 3 microarchitecture. Not bad for an microarchitecture that is not bringing any radical improvements, eh?

Meanwhile, AMD is touting an even more impressive 31% IPC improvement in AI workloads. This more extensively leverages some of the ISA improvements in Zen 6, which has seen AMD add some new instructions that are particularly useful for AI workloads.

As for the fine print on these claims, AMD notes that these measurements are taken in a fixed frequency scenario, comparing a Zen 5 chip to a Zen 6c chip. The big-to-small comparison may look a bit odd at first, but since AMD is giving Zen 6c more L3 cache in this generation, finally bringing it on par with the big cores, even that distinction is going out the window. Which means Zen 6c versus Zen 5 comparisons are more valid than ever. Still, as no Zen 5 part had 16 cores in a single CCD, these metrics are also comparing a two CCD design to a one CCD design, which means that the newer microarchitecture is further benefitting from avoiding the performance cost of heading out to the IOD and back to hop between CCDs – a benefit that is not stemming from the CPU core design itself.

Zen 6 ISA: More AVX Math, and AMD Gets FRED

Speaking of those higher IPC improvements for AI workloads, let us take a look at some of the new instructions Zen 6 supports that is helping to fuel those gain.

Among new instructions supported by the Zen 6 microarchitecture are additional AVX instructions for INT8 operations, format conversion, and integer fused multiply-addition (this one being something Intel first pioneered). Along those lines, the AVX pathways are also getting full FP16 support here, giving Zen 6 the ability to handle dense FP16 operations the same way it can handle FP32 and FP64 today. Finally, AMD is introducing a new bit matrix multiply instruction to the AVX-512 ISA in order to further speed up specific bitwise matrix operations.

And while not directly CPU core performance related, the Zen 6 microarchitecture also introduces some other new instructions for other use cases. This includes a trio of new kernel instructions for virtualization, the most interesting of which is Flexible Return and Event Delivery (FRED), a new-to-AMD interface for transitioning among kernel levels. Speaking to Mike Clark, the architect was especially excited about this one, and we are told this should make a big impact going forward.

Finally, for programmers who are looking to make the most of their software on Zen 6 chips, AMD has a couple of new toys for them as well. Most notable here is the addition of buffering for instruction-based sampling. Memory gets some consideration as well with a new memory profiler.