Setting the Background: How Intel Xeon Dominated
The golden age of Intel Xeon was the Xeon E5 family. Some may say it started just before, some may say it continued a generation after. What is clear, is that the Intel Xeon E5 V1-V4 families were dominant. From Q1 2012 to Q2 2017, these chips gave Intel an enormous market position reaching over 95% of servers sold.
Intel’s big innovation was to move the traditional northbridge functions onto the chip, leaving the southbridge for lower-value I/O. PCIe lanes were integrated into the CPU silicon which meant Intel had an efficient PCIe device-to-device path as well as the main system memory to PCIe device path. The Intel Xeon E5-2600 CPU was a stake in the ground that the CPU was the center of the server.
At the same time, with the loss of competition as AMD largely bowed out of the market during this period, Intel’s designs pursued an incremental improvement plan. IPC grew modestly. Core counts went form up to 8 cores in V1 to up to 22 cores in V4. Memory transitioned from DDR3 to DDR4 and increased in speed. PCIe lanes were set at 40 and that was set. For server vendors, this stability meant that designs lasted a long time. When you have a similar memory, PCIe, and socket footprints, form factors do not need to change. The standard dual-socket server became dominant.
The Intel Xeon Scalable family proved anything but its namesake. If we remove the Intel Xeon Platinum 9200 given that it is focused as a HPC-only part, this is what happened to the core count increases over time for CPUs designed for mainstream dual-socket server use.
Once we hit 2017 with Intel Xeon Scalable, the Intel bars stopped getting larger for the first three year period in the last decade. AMD could claim more cores when it launched Naples, but Intel could claim the per-core performance crown from Intel in 2017 and even pushed clock speeds in 2019.
In early 2019, the AMD EPYC 7371 launched with top-end 16 core performance that beat Intel’s offerings at the time in the SPEC CPU2017 integer benchmarks. Aside from that SKU, for the most part Intel has been able to say we do more with slightly fewer cores during 2017 through the first quarter of 2019.
When the 2nd Generation Intel Xeon Scalable launched last quarter, the top end core counts did not change, but the mainstream “heart of the market” SKUs saw a massive performance jump due to core and clock speed increases of 30% or more. You can see our Intel Xeon Silver 4210 Benchmarks and Review, Intel Xeon Gold 5220 Benchmarks and Review, and Intel Xeon Gold 6230 Benchmarks and Review just to show some examples. For the majority of the market that buys in this range rather than top-bin SKUs, Intel delivered a massive performance boost at the same price level.
By increasing IPC, adding a massive amount of cache, adding PCIe Gen4, and doubling core counts per socket, AMD has changed the game on Intel. What it is doing goes beyond just a mere core count upgrade. AMD is building the best server platform, with a lot of x86 CPU cores attached.
The 2019 2nd generation Intel Xeon Scalable family still has its legacy platform controller hub or “PCH” architecture just as it did in the Intel Xeon E5 era, dating back to 2012. This PCH is codenamed “Lewisburg” and you can see that in server configurations commonly as the Intel C621, C622, and etc. PCH options.
AMD’s approach is different. Ever since the company’s 2017-era “Naples” generation arrived, it no longer requires a separate PCH. The PCH uses motherboard PCB space, it is an additional cost of Intel platforms, and it adds power consumption. The reason we test power at the PDU rather than at the CPU socket level is that we went through this transition when Intel ditched the northbridge in 2012 and saw significant savings over AMD’s designs of the day. This time, it is AMD with a more integrated solution.
There was another difference. Intel was able to point to its single monolithic die and basque in the glory of being able to manufacture a marvel of engineering. To be clear, it is a feat to do what Intel does. AMD instead decided that it was time to go to a chiplet architecture packaging smaller, easier to manufacturer dies together.
You can see more about the multi-die versus monolithic die architecture here:
The world has certainly changed. AMD EPYC 7002 “Rome” now brings a better chiplet design. Intel is also not saying AMD “glued” together parts anymore. Instead, Intel is trying to catch up with the Intel Xeon Platinum 9200/ Cascade Lake-AP family gluing two pieces of silicon together and losing some functionality. Intel is also aggressively marketing its packaging technology advantages and we expect to see Intel Foveros solutions out later 2019 in other segments.
As we enter Q3 2019 a few things are clear:
- Monolithic large die CPUs are moving to multi-chip
- Servers are becoming more disaggregated
- Dual-socket server may give way to single-socket servers
With its new chiplet and I/O chip design, the AMD EPYC 7002 follows this trend. Making its I/O chip the center of a server means AMD has greater design and manufacturing flexibility which is changing the game for server vendors, peripheral suppliers, and customers in the market. Let us pivot and take a look at the AMD EPYC 7002 series.