Delving into the Devilish Chip
There has been a lot of debate regarding the accuracy of the IC’s shown in Bloomberg Businessweek’s story. What the publication never produced is pictures of the actual chip. This is despite the fact that allegedly this happened well into the era when cameras in phones were ubiquitous and at a company that has been making cameras for decades. Allegedly the servers were not only observed in data center red zones with no cameras allowed but also at other facilities. None of the seventeen alleged confidential sources seems to have produced an actual photo of the device. The descriptions of what the chip actually did were not cohesive from a technical standpoint, but we can summarize what would have had to happen for this to work.
The Cover Image – A Really Small IC Functions
To those who are not technically minded, which is most of Bloomberg’s distribution, the picture of a small chip with no details seems scary. Something has been the talk around tech watercoolers: what does the chip do? We are going to get into some of the inconsistencies on how Bloomberg describes the chip later in this article, but let us assume for a moment that someone would make a chip in the name of espionage. Here are some of the basics of what it would need to do:
- Get power so as not to mess up other traces. Without power, electronics do not function.
- Receive this power without requiring additional components to be added to the motherboard such as capacitors or resistors. Bloomberg never stated multiple packages were added.
- Store payload on the chip package that survives long periods of power off during shipping. This likely requires persistent memory cells such as NAND plus some controller logic to read back the voltage levels or to put and get data from the storage.
- Initialize immediately since it needs to beat the BMC’s initialization speed to deliver a payload.
- Tap into wires on the motherboard to see that either the main system (CPUs) or BMC has started.
- Identify an event in the system to activate if it is waiting for a sequence.
- Deliver the payload.
- Continue delivering payload through firmware flashes and security fixes.
- Likely requires logic circuits to do this. For performance (since it has to beat the BMC) it may need some local cache.
- Needs to do so in a way that evades the firmware teams. If signals come off of serial buses during BMC boot, the firmware teams can see this.
At a recent chip conference, a discussion was around whether the chip can be truly dumb and simply transfer data directly. This greatly limits the silicon needs if it can simply power on and start delivering the payload. To draw an analogy, this would be like setting a trap to go off at a specific time on a road, and hoping that you caught a single snake slithering by. If you were slightly late on your timing, since you are not processing where the snake is, you may only catch its tail. If you missed by a bit more, you would miss the snake completely. If you want this to work, you need some minimal logic.
Indeed, Bloomberg validates most of this list of capabilities. In their article image, they stated these chips even have networking capabilities.
As a quick note to our readers, this is actually extremely similar to how you would describe an entire BMC complex. There are some low power cores, memory, and networking capabilities. Server BMCs are multiple packages, each component is many times larger than the chips Bloomberg describes.
The signaling coupler may be a stock image, but networking is important. First, adding die space for even a network MAC would take up silicon real estate in an extremely constrained design. Second, 1GbE, a low-speed networking standard, uses four wire pairs to transmit and receive data. The KX variants of Ethernet implementations for blade chassis, like the Microblade shown, can have one to four lanes of differential pairs for traversing PCB. That adds eight wires to the chip design. Also, these wires would need to be attached, through the PCB, to some external port so they could communicate with the outside world. The chips pictured in the article, are smaller than 1GbE network controllers used today, even those with low functionality and buffers.
If these chips had a networking capability, it would be nearly impossible for them to get a network uplink. PCB designs would be too sensitive to run networking wires to external ports without major changes to the PCB. That would also likely have signaling impact and be immediately detected.
Even if we assume networking was an error since it makes little to no sense in this context, a chip with this much functionality raises more questions.
Who is Involved in Chips?
Assuming the Bloomberg’s article is true, there is a more precarious line of questioning to embark upon. Namely, who fabbed the chip? Chips do not appear out of thin air. They have to be made somewhere.
The chips Bloomberg describes are immensely tiny. For a sense of scale, here is a penny and a pencil on a dual BMC Microblade complex, a node that works in the same chassis and uses the same BMC generation as Bloomberg depicts. The package with processing power, networking, and memory needs to be smaller than any chip you can read the label on in this picture (actual hardware, not a rendering.) On the far left is a Realtek 1GbE NIC. The ASPEED AST2400’s are the BMCs with low power Arm cores. The Winbond packages are the BMC RAM also known as memory in systems. The point is, to combine even less powerful elements of each into a package with the functionality Bloomberg describes, it would require amazingly small lithography techniques. I have yet to find someone able to say that adding processing power, signaling interfaces, networking (even a MAC), and memory/ storage onto a package this size is even possible and I have asked folks in the valley that do this at major companies.
Since this chip most likely needs to be on today’s leading silicon process nodes, let alone what was available years ago, there are only a few companies capable of producing leading node products in the 2014 timeframe. Some of these include:
- Global Foundaries
You might even go to IBM, UMC, SK.Hynix, Toshiba, STM, or SanDisk/ WD as potential foundry partners even though they either specialize in creating economies of scale around a few standard products, do not typically produce logic elements, or tend to be behind on the absolute most current generation technologies. Bloomberg’s article says that China made the chips.
China has a “Made in China 2025” program where a goal is to get leading-edge process technology in-house. You can see how this is progressing in our article YMTC Xtacking 3D NAND Launched. In 2014, it would likely have to be one of the companies above not a Chinese fab since China, at the time, did not have the level of process technology required to make a chip like this. Of course, some specialize in DRAM, others in logic, others in NAND. If you believe the chip required NAND and logic, then that list shrinks considerably. If you take “memory” to be DRAM which would be the common usage in the industry with NAND being “storage,” then the shortlist would change.
Here is the point. None of those companies listed above in the 2014 list are based in mainland China. All of the companies on that list are heavily relied upon by the industry to make the infrastructure many take for granted today. Furthermore, it should be nominally difficult for any of those companies to find wafers of extremely small chips in their production logs. Most lower functionality chips are produced on older generation process nodes.
The newest process nodes generally are used for high-value chips that are found in mobile phones, PCs, servers, FPGAs, and elsewhere that can support high cost per die area. In a $3000 server processor, higher manufacturing costs are acceptable if they allow you to get a competitive advantage since the margin and ASP are high. In a $2 IC package, adding another $0.20 of manufacturing cost is likely enough to make customers look elsewhere. This would be something that size wise looks like a $2 or less IC, yet is produced on a line that is also putting off much larger, more complex, and more valuable packages.
While it seems likely that very small chips exist, during the time period in question, there are likely only a few foundries that could put the functionality listed above in such a small package. Even if one could design a chip that fit into such a small package, getting it made is another challenge.
Why Go Physical?
A hardware hack seems scary. It is really good for page views. On the other hand, in the timeframe that was proposed in the mid-2010’s, there was an easier way: do a software firmware hack. There are hundreds of examples of these to the point that they are not exciting. They are also the attack vendors some of the companies who responded to Bloomberg seem to think that the reporters were referencing. There are a number of advantages such as one would not need to:
- Spend months designing the chip, getting wafer starts at a foundry, then getting it packaged
- Transport the packaged products
- Infiltrate the factory and have chips added
- Alter motherboard designs
- Leave a physical trace
The first four items there are likely good enough. As we showed with iDRACula and has been shown on HPE iLO and Lenovo IMM as well, BMCs of the era in question were easily exploitable via software, and one can insert persistent software into them. If one can do it in software, there are a lot of logistics issues that they can avoid by going software rather than hardware.
Perhaps the last one is the most intriguing, not leaving a physical trace. Assuming Bloomberg correctly stated it has sources that found hardware there is one somewhat obvious detail missing. Who made the chips? If they were found, then it is reasonable to assume that one would try to figure out which foundry made it. In the silicon industry, there are firms that will open the package and work microscopic magic on them to determine process steps and techniques used to create a chip. These firms are able to identify key features being used, and thus who made the chips.
If you were doing an investigation, this is the hard evidence trail to follow. Figure out where the chips were made and that leads to a trail. You could then request information from the company who made them. That would allow you to get details on who paid for the chips, who sent the designs, where the chips went after they left the fab. You may even be able to get documentation for your team analyzing the hardware if you pressed hard enough. Bloomberg said its sources had knowledge of an investigation into Supermicro’s supply chain, but the other obvious vector is the chip’s supply chain in the hope that they would meet somewhere.
Physical hardware has a physical trail and it is relatively easy to follow. Interestingly enough, Yossi Appleboum, one of Bloomberg’s sources for its follow up article, noted in our interview that physical alterations in the production of servers would be easy to trace. We are going to discuss how Mr. Appleboum and other sources disagree with the conclusions drawn by Bloomberg later.
On that note, let us take stock at sources that Bloomberg Businessweek has disclosed.