During Arm TechCon 2019 something was conspicuously absent: big server cores. This was something we wanted to see, but during the show, a few things became clear. Next-gen parts are coming. We should hear more from Fujitsu, Marvell, and potentially Ampere at SC19 in November. It also sounds like Arm largely figured out that it has a potentially strong market: the emerging edge. With the Arm Neoverse Brand about a year old, and the next-gen to ship products based on N1 Ares cores, Arm may be focusing more on a larger edge build-out.
Neoverse at TechCon 2019
To be clear, we asked, both Ampere and Marvell and eMAG 2 and ThunderX3 are firmly in the pipeline and we expect to hear much more about them in the coming months, especially in 2020. Arm has made big investments in both companies which is perhaps as far as Arm can go without making chips themselves and scaring their entire ecosystem into thinking that Arm is going to start selling chips. At this point, a chip startup in the Arm space for the traditional data center market is competing with Arm’s backing of Ampere and Marvell, along with Huawei, and Fujitsu. All of whom have experience with previous generation silicon.
Arm had an infrastructure section on the TechCon 2019. In fact, our AoA Analysis Marvell ThunderX2 Equals 190 Raspberry Pi 4 analysis was presented by Marvell (we had no heads-up on this so did not get a picture) during one of the breakouts. Along with hardware vendors, ecosystem partners ranging from Docker, VMware, and NVIDIA were talking about how they are enabling their technologies with Arm. At this point, table stakes such as having Ubuntu and RedHat OSes and mainstream components like nginx have all been anted by the ecosystem. Adoption in the data center is largely down to performance and TCO hopes in future generations.
On stage at TechCon 2019’s various keynotes, mainstream Arm data center CPU support was conspicuously absent except one salient point with this as the background:
Arm said in 2020 we will see 64 core CPUs (Huawei Kunpeng 920 64-Core Arm Server CPU has been announced). Where Arm is gaining a lot of momentum is in applications such as SmartNIC. As we see SmartNICs are taking advantage of Arm cores. Here are a few examples we have covered recently:
- Mellanox Bluefield-2 IPU SmartNIC Bringing AWS-like Features to VMware
- Xilinx to Acquire SolarFlare for SmartNIC Capabilities
- Packet Launching Microservers with Netronome SmartNICs
Here, this makes a lot of sense and is also what Arm is highlighting. Arm is enabling expansion of silicon TAM by making (largely x86) servers do more through SmartNIC (Arm core) offload.
For now, it seems as though Arm sees attacking the edge CPU and accelerator markets as a much easier market to break into versus the traditional data center CPU market. We are already seeing Arm cores in BMC’s including the newly launched and soon to be popular Aspeed AST2600. Even the AMD EPYC 7002 series includes an embedded Arm core. Intel is still using embedded Quark core IP in the current generation Lewisburg PCH, but the company is using Arm already in products like its Stratix 10 and Agilex FPGAs. Perhaps a resurgent Intel will re-think Quark.
The key here is that Arm is making headway in the data center, just not in the headline sockets.
Perhaps this is the entire point. The primary CPU market in traditional markets is going to be difficult to break into. AMD in 30 months has disrupted this market where Arm’s partners are not making a significant dent, yet. It seems as though Arm’s strategy is to move up from the IoT edge and mobile into the 5G edge infrastructure. In the data center, the short term plan seems to be securing wins to besiege Intel and AMD’s CPUs before taking those sockets in future generations. We think that is a less exciting story, but it is one that carries an enormous TAM as it is easier for Arm to gain market share in a net-new 5G built-out versus unseating an existing incumbent infrastructure. Luckily for Arm, it has a vibrant partner ecosystem crafting unique point solutions for these markets.