At SC22, Intel showed a bit more on its upcoming Falcon Shores XPU. This is Intel’s platform for accelerated computing in a few years. We first discussed Falcon Shores at SC21 last year in our Raja’s Chip Notes Lay Out Intel’s Path to Zettascale. We have been getting more including at Intel’s ISC 2022 Keynote.
Intel Falcon Shores XPU Update at SC22
The new diagrams are very interesting. With Falcon Shores, Intel is showing the integration of x86 cores and Xe cores along with memory. The fact that Intel, AMD, and NVIDIA are all looking at some form of this architecture in the next 3 years instead of the traditional mainstream CPU plus GPU model is telling.
Intel is showing the Falcon Shores XPU with x86 only tiles, x86 plus Xe tiles, Xe only tiles, and then with different custom IP along with the x86 cores. Imagine for a national or regional HPC effort being able to design the accelerator core, but then having it integrated with a standard Intel x86 core.
While this is exciting and makes sense given Intel’s strategy, the perhaps more interesting piece of this will be all of the interconnects and I/O that go into these chips. Co-packaging compute like this is designed to lower the cost of moving data. It also makes systems scalable by having integrated compute units. How this all connects and what one can do with Falcon Shores lines is going to be what will be the most exciting aspect of the line.
This is the one to be really excited about. Intel’s Falcon Shores is like a second/third generation APU/XPU product. AMD will have its MI300 likely in 2023. NVIDIA is pushing with its Arm Neoverse V2 cores for NVIDIA Grace. Intel’s solution is planned to have things like Lightbender silicon photonics interconnects (perhaps with the new connector?) that will allow for different designs. Having custom IP integration also follows the company’s goal of becoming an integration house while giving a nod to geopolitical asks for local IP used in supercomputing.