Recently we were at OCP Summit 2017 and had the opportunity to see more progress on the AMD Naples platform first hand. AMD Naples is a highly anticipated server platform from AMD that is set to challenge Intel Xeon dominance in the x86 2P market later this year. As far as we are aware, there have only been two AMD Naples platforms publicly shown to date and we have pictures of both plus a block diagram showing how the 128 lanes of high-speed I/O are implemented in an example Naples platform. While headlines of 128 PCIe 3.0 lanes for the platform are attention grabbing, realistically many of the I/O lanes will be used for other system I/O purposes. The block diagram shows how these platform I/O needs can be met with 112 PCIe lanes available to PCIe cards, NVMe drives and etc.
Publicly Shown AMD Naples Server Platforms to Date
The first publicly shown AMD Naples platform was the AMD Speedway system. Here is a snap we took at the AMD Tech Day in San Francisco earlier.
You can read some of our analysis of the platform in our earlier AMD Naples piece.
At OCP Summit 2017, Microsoft and AMD showed off a Project Olympus – AMD Naples server. For reference, the system on the right edge of the below is a Qualcomm Centriq 2400 system and the system on the left is using a not yet formally announced Intel CPU (e.g. an OCP Project Olympus Skylake-EP / Purley server.)
You can see that the platform has several PCIe x16 slots, SFF PCIe connectors, and plenty of room for m.2 NVMe SSDs.
The platform to the right has the CPU socket covered (here is essentially what it will look like), but you can see the 32 DIMM slots of the Naples platform push the bounds of the width of the chassis more than the upcoming Intel platfrm.
We also have a clear picture of an ASPEED BMC in the center of the PCB. Our initial analysis of the AMD Speedway platform showed that although AMD is claiming that Naples is a SoC design, the external BMC will still be part of the platform. Looking at a block diagram of the server platform gives us a clearer view of what is going on.
AMD Naples 2P Server Block Diagram with 112 PCIe Lanes
We also have a full AMD Naples dual socket block diagram from the company. Note, different servers will use different implementations, but this is an example of how Naples can be implemented. This shows 16 DIMMs per CPU, 32 DDR4 DIMMs on the platform using two DIMMs per channel.
Perhaps the most interesting piece of the block diagram is that the dual socket server still has 112 lanes of PCIe 3.0 available even after using high-speed I/O for USB ports, the BMC and other system components.
The block diagram also shows a 4-XGMI link between the two CPUs. Each CPU has 128 lanes of high speed I/O with 64 dedicated in each for chip to chip communication in dual processor configurations.
The impact of having 112 PCIe 3.0 lanes available cannot be understated. Current generation Intel E5-2600 V4 dual socket platforms only have 80 PCIe lanes available. While AMD may market 128 v. 80, that is not a realistic number. Based on the platforms we have seen, and the block diagrams, we see that 112 PCIe lanes in a system is a more reasonable figure. On the Intel side, Xeon E5 V4 platforms normally will not use its PCIe 3.0 lanes for the BMC, USB, SATA ports and etc. because there is a PCH. As a result, the comparison we will be using at this point is 112 v. 80 or 40% more usable CPU PCIe lanes for AMD Naples versus Intel Xeon E5-2600 V4.