Today we get to share a story that we have been sitting on for weeks, AMD Naples. Naples is the codename for AMD’s newest Zen architecture server platform. With Naples, AMD is clearly pushing ahead in one key area: I/O. From what we have seen, Naples is going to be a more expansion friendly platform than the current Intel Broadwell-EP generation of servers and more than we have seen from initial Skylake-EP “Purley” platforms as well. Based on what we have seen with AMD Zen-based Ryzen desktop performance Naples is going to be a lot more competitive than we previously thought. Hopefully, Ryzen desktop parts will help eliminate future Zen/ Naples headaches e.g. Ubuntu, CentOS, VMware and etc. We are going to give a quick overview of the Naples platform.
AMD Naples Overview
At the AMD Tech Day in San Francisco a few weeks ago, AMD presented Naples to a technology analyst and press audience. The clear focus was on gamers given the immediate launch was for Ryzen, the consumer desktop part. Although this slide came at the end of a presentation by Forrest Norrod’s, SVP and GM of Enterprise, Embedded, and Semi-Custom Business Group at AMD, we thought it highlighted the key points of Naples. Zen is simply going to offer more cores, more memory bandwidth and more I/O than Broadwell-EP and quite possibly the upcoming Skylake-EP.
First off, Naples is going to be a 32 core, 64 thread design.
It is also going to utilize an 8 channel DDR4 memory controller. We were told at the event to expect two DIMMs per channel (2DPC) designs which means it can support up to 16 DIMMs.
We wanted to pause here and show why these numbers are relevant. AMD’s CPU Complex, CCX has four cores, 8MB L3 cache. An 8-core Ryzen based CPU is 8 cores, 16 threads with 16MB L3 cache, or two CCX’s. It also has a dual channel DDR4 memory controller.
If you do the simple math, with 32 cores, 64 threads, 64MB L3 cache and 8 DDR4 DIMM channels, the basic formula for AMD’s Naples platform looks similar to four Ryzen 7 CPUs.
Then we get to I/O and things change slightly. A Naples chip has 128 lanes of high-speed I/O. Much like we see with Intel chips such as the Intel Atom C3000 series (and we foreshadowed that we will see in Skylake-EP), the trend is to give platform designers fast pipes, then let the vendor customized how the pipes are configured. On AMD’s Naples platform, an OEM will have 128 lanes of high-speed I/O for storage, networking and PCIe expansion. If you wanted a clear picture of why this will be exciting, this is the picture for you.
As you can see, the prospect of having enough PCIe lanes for a full 24 bay NVMe server with x4 PCIe 3.0 lanes is now in sight, with additional lanes left over for boot drives and high-speed networking. While that sounds great, we wanted to do a quick view of what happens when a second CPU is added.
With a second CPU, 64 of the 128 lanes from each CPU are used for what AMD calls “Infinity Fabric” which is the interconnect between the two chips. In a dual socket system, that means there are still 128 lanes available, 64 from each chip.
There are some practical implications to this. It means that if you wanted a less complex system, avoiding the fabric and getting high I/O, you would likely opt for a single CPU Naples platform.
Live AMD Naples Dual Processor Hardware
We did get to see actual AMD Naples hardware in the form of AMD’s reference Speedway development system. As you can see, each AMD Naples CPU is flanked by 16x DDR4 RDIMMs. The entire setup takes the width of the rackmount server.
You can see that the development platform has SATA ports via SFF-8087 cables. It also has an absolute ton of PCIe x16 slots. For those working on machine learning or large VDI clusters, it is clear AMD is enabling Naples to use many of their GPUs with their server platform.
AMD did show off benchmarks of the AMD Naples platform versus an Intel Broadwell-EP platform.
You may see the results of these benchmarks but we are not going to show them. For example, in the third demo they showed the Intel system failing to load a memory intensive application, but it appeared as though it was just a problem size larger than 384GB and less than 512GB. That meant that the Intel demo system failed while the AMD system, that AMD configured with more RAM, was able to complete the task. At STH, those types of results are not fit to publish.
The one part that was clear in the presentation is that the AMD Naples platform is going to get integration with the Radeon Instinct line of GPUs, including future Vega based products. There is good reason why AMD wants more PCIe I/O lanes, more GPU sales.
That is the basic AMD Naples overview but we wanted to look into one aspect mentioned on the slides. The notion that the AMD design was a SoC. If you look at the Speedway platform, one feature we noticed missing was a south bridge/ PCH. On the Intel side these parts are currently the Intel C612 PCH on Haswell-EP and Broadwell-EP. Since the I/O is coming from the chips, there is no need for a PCH with AMD.
The next question we had was looking at the rear of the AMD Speedway Naples development server. One can see two USB 3.0 ports. There is a SFP+ 10GbE port and a RJ-45 port.
What caught our eye were the serial ports and VGA ports. It is unlikely AMD has near “ancient” I/O as part of their design. We looked back at the photos we took while talking to AMD representatives (sorry not the best) and caught this glimpse:
As you can see, there is an Aspeed BMC above the two rubber bands on ribbon cables. One can also see that there appears to be an Avocent license sticker. We saw that management solution used in Gigabyte motherboards for example. What that seems to indicate is that the BMC functions, at least on the development platform, are not Naples chip based and instead are using an external BMC. From an integration standpoint, this is a good thing as it means that standard IPMI and Redfish APIs and tools should work with Naples.
There is one thing for sure, AMD Naples is going to be an exciting platform. We did ask AMD representatives at the Ryzen Tech Day about the possibility of fitting 4 nodes in 2U and were told that vendors had designs ready. The I/O situation is intriguing as with 128 lanes of high-speed I/O the AMD architecture could be a winner in terms of expansion and for tasks like GPU or FPGA platforms. The notion that AMD Naples will not be competitive with Intel Skylake-EP is completely false. There are broad swaths of the market where AMD Naples is going to provide an equal or better platform than what Intel Skylake-EP will offer. With that said, Intel has deep relationships with server vendors. Let us not forget that AMD essentially abandoned its server partners since the Opteron 6300 release. Relationships in this industry run deep. Luckily, we will get to see more of AMD Naples as it launches in Q2 2017.