AmpereOne M Finally Brings the Big 12-Channel Socket to its Arm CPUs

Ampere Computing launched its AmpereOne Arm server CPU in December (but made more information available this week) with a twist. Instead of 8-channel memory in the standard AmpereOne, this new “M” version adds 12-channel memory. That socket upgrade allows it to get closer to feature parity with the AMD EPYC 9005 Turin and the Intel Xeon 6900P. Let us get into what was announced.

AmpereOne M Brings the Big 12-Channel Socket to its Arm CPUs

Taking a look at Ampere’s 2024 roadmaps, the AmpereOne M was clearly there. Just for some sense of how long this platform has been anticipated, we saw the 12-channel Ampere platform at Computex 2023 in rooms where we could not take photos. In Q2 2024, the roadmap picture made it seem like the 12-channel platform and CPUs for that platform were generally available.

The next quarter in August 2024, we saw that the AmpereOne 12-channel DDR5 platform, dubbed AmpereOne M, would be shipping in Q4 2024 instead. We covered this in our Ampere AmpereOne Architecture at Hot Chips 2024 piece.

In terms of SKUs, it seems like Ampere is keeping a relatively smaller SKU stack for its new 5nm chips. The naming seems to be A then the core count – clock speed then an M for being AmpereOne M.

The 192 core part aligns with the top-end AmpereOne 192 core SKUs we have looked at previously.

For those wondering, the additional memory channels need a different socket, but Ampere is using I/O and memory controller tiles around its main compute and cache tile. AmpereOne was designed to expand to the second platform quickly by adding more memory controller tiles. Here are the two I/O chiplets that AmpereOne uses:

Here is a quick look at the specs. Interestingly, AmpereOne is supporting 12 channel memory at only 1 DPC. We discussed why 1 DPC operation was going to be more relevant going forward. Also interesting is that this only supports DDR5-5600. Intel is using DDR5-6400 in its P-core parts along with MCRDIMMs/ MRDIMMs for high-speed 1 DPC in 12 channels. Sierra Forest, although only 144 cores in the Xeon 6700E series with 8-channels of DDR5 can operate at DDR5-6400. Even the 192 core/ 384 thread AMD EPYC Turin is up to DDR5-6400. Those were all parts made available in 2024, so in May 2025, the DDR5-5600 12-channel configuration stands out. Perhaps that is due to the difference between roadmap and when these are “launched”.

Another key spec is that the PCIe connectivity can bifurcate down to PCIe Gen5 so it can directly handle occupying its lanes with standard PCIe x4 NVMe SSDs (although x2 bifurcation for active-active NVMe storage is still missing. That is different than NVIDIA Grace.

Final Words

This year, we got the news that Softbank was acquiring Ampere. It feels like Ampere is moving into a mode where it is going to be changing focus. We could not find an announcement with a customer or partner listed for platform availability on Ampere’s site nor a launch customer quote. We usually assume Oracle is a customer, and we saw motherboards for this two years ago, so it feels strange to have nothing. Perhaps that is a product of the acquisition. NVIDIA Grace-Grace is not an ideal enterprise server CPU. That leaves the enterprise server Arm market solely the domain of Ampere. When a chip company launches a new platform, server vendors are not rushing us samples to use, and there are no customer/ partners online it feels strange.

I just hope we get to see these working in-person one day.