At Hot Chips 30 we had the opportunity to talk to Akhilesh Kumar, the architect of Cascade Lake-SP and we had the opportunity to sit through the presentation. We covered much of this at the Intel Data-Centric Innovation Summit a few weeks ago but there were a few new disclosures at the show. The key theme seems to be that the Intel Xeon Scalable platform is not so “scalable” after all.
Cascade Lake Incremental Update over Skylake
First off, we want to thank Akhilesh. He did a great job in his briefing, his presentation, and the questions that arose afterward. He was in the unenviable position of being the chip architect announcing what amounts to a bug fix chip, at a chip conference, and instead of having to talk about Optane Persistent Memory. He displayed absolute grace in handling the task. The thrust of Intel’s message was simple: Cascade Lake-SP, from a compute perspective, is a bug fix chip.
Here is the Intel Xeon Scalable Cascade Lake-SP summary. The platform and performance boosts are at the bottom for a reason.
We are going to work from the bottom up. Talking about the basic x86 core specs themselves, then moving up to the mitigations, the new VNNI inferencing extension, and Optane Persistent Memory.
Intel Cascade Lake-SP Base Specs
Here are the setup slides around Skylake-SP and the scalable platform:
We are not going to put much text here so that you can see the side-by-side with Cascade Lake specs.
The first bullet is the eye-opener. We have known 28 cores were going to be the answer for some time. Cascade Lake-SP will offer the “[s]ame core count, cache size, and I/O speeds as the first-gen.” That means up to 28 cores maximum, the same size cache. It also means the same PCIe 3.0 x48 per CPU. DDR4 will be limited to 2666MHz as it is today. UPI for socket-to-socket communication will sit at 10.4GT/s, the same maximum as today.
While Intel will have room for some additional speed bumps, it will have to add cores in another way. We think that if Intel increases core counts, it will add cores at a SKU level, much as it did between, say the Intel Xeon E5-2630 V3 and V4 generations. There the CPUs went from 8 to 10 cores at the same micro-segment.
Later in this article, we are going to show what that means for Intel looking across previous generations in the section “My Challenge to Intel.” Next we are going to look at some of the side channel mitigations, VNNI, and Optane Persistent Memory. Then we are going to wrap up with analysis and final thoughts.