This is a big one in the industry. Version 1.0 of the PCIe 4.0 spec has been officially released. In the server industry, PCIe 3.0 is absolutely constraining I/O in modern systems. For example, PCIe 3.0 cannot handle dual 100Gbps NICs. Likewise, NVMe SSDs are stuck with the transfer rates of PCIe 3.0 speeds for the time being. PCIe 4.0 promises to just about double the transfer speeds for PCIe devices so this is a major win. We had heard rumors that either Intel or AMD were thinking of supporting PCIe 4.0 in their 2017 server products. Unfortunately, the spec was released after this last generation. At the same time, we see IBM, Mellanox and others embracing PCIe 4.0.
We are going to copy the press release below but there is a line at the end that is telling: “PCIe 5.0 specification, targeted for Q2 2019” is only about six quarters away. PCIe 3.0 in comparison was released in 2010. So we are moving from a seven-year cadence to a six-quarter cadence. The reason for this is simple. PCIe 4.0 is already too slow. Major data center operators such as Google and Facebook are pushing for 400GbE and Mellanox is looking at HDR Infiniband in 2017-2019 and NDR Infiniband in the next few years. SSDs are completely limited by the PCIe bus and have already started migrating to DRAM channels to get higher bandwidth and lower latency.
The bottom line here is that while PCIe 4.0 will provide some release, the industry desperately needs PCIe 5.0 for devices on the near-term horizon.
PCIe 4.0 Version 1.0 Press Release
Here is the official release via the PCI-SIG:
I’m pleased to share that PCI-SIG has released the PCIe 4.0 Specification Version 1.0 and it is now available for download on our website. We had previously announced in June this year at our annual DevCon event that the Version 0.9 specification was feature complete and undergoing member IP review. The final published spec describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant.
The delivery of the PCIe 4.0 specification to the industry is an important addition to our spec library as it delivers high-performance 16GT/s data rates with flexible lane width configurations while continuing to meet the industry’s requirements for low power. Additional functional enhancements include:
- Extended tags and credits for service devices
- Reduced system latency
- Lane margining
- Superior RAS capabilities
- Scalability for added lanes and bandwidth
- Improved I/O virtualization and platform integration
And we’ve seen unprecedented early adoption! Prior to publication, we’ve had numerous vendors confirmed with 16GT/s PHYs in silicon and IP vendors already offering 16GT/s controller. Given the interest, we held a pre-publication Compliance Workshop with preliminary FYI Testing Only for PCIe 4.0 architecture that attracted dozens of solutions. We’re continuing to conduct FYI testing in our workshops throughout the remainder of the year.
PCI-SIG members are welcome to access the PCIe 4.0 spec online at no cost through the PCI-SIG Specification Library. Non-members may purchase the specification here.
PCIe 4.0 is a significant milestone, but we’re not resting. We’ve already released the Version 0.3 of the forthcoming PCIe 5.0 specification, targeted for Q2 2019, which will increase speeds to 32GT/s. For more information on PCI-SIG or PCIe technology, visit our website at www.pcisig.com.
Do you know if there is a realistic expectation that PCIe 5.0 is going to continue to use the standard copper traces in a regular motherboard or are they going to have to go optical or at least use some type of shielded cable for data signaling instead of motherboard traces?
That could be a big factor in giving PCIe 4.0 a longer practical lifespan even if 5.0 gets ratified as a standard relatively quickly. Obviously there are some use-cases like 400Gbit/1Tbit/etc. networking hardware that can never get enough bandwidth but even in data centers not everybody needs that much bandwidth, especially if it requires more exotic hardware.
I don’t see anything about changing transmission medium in the current version of the 5.0 base spec. Still NRZ, still 128b/130b. Signal integrity with 32Gbit/s NRZ is gonna be nasty, though. It’s hard enough getting the 25Gbit/s signals for QSFP28 to travel moderate distances.
I didn’t think that anyone will use PCIe 4?
assuming the transition to a new platform takes as long as last time we likely won’t see 4.0 in x86 platforms. It’s planne for POWER9 though.
Doesnt AMDs Infinity Fabric run through the PCI-E bus? If so, you’d think they’d jump on this pretty fast.