Enter the Arm AGI CPU, Arm’s First Data Center Production Silicon
Earlier in 2026, I attended the Arm AGI CPU launch in San Francisco, California. This was where Arm officially unveiled the AGI CPU on stage.
The CPU itself was quite impressive for early 2026. It included a newer-generation CPU core based on Neoverse V3, and it had up to 136 of those cores. I/O was next-generation as well, with 96 lanes of PCIe Gen6 and CXL 3.0 support. CXL has swung back into favor as hyperscalers look to the technology to reduce memory costs. It also supports DDR5-8800 for high memory bandwidth.
At the base of the Arm AGI CPU, two Arm Neoverse CSS V3 chiplets connect to deliver up to 136 cores. Arm has a SKU stack, but this is the headline feature. You may see the CTSS chiplets, each with what look like 70 cores, and all of the surrounding IP blocks. That gives you some idea of just how far this is from licensing a single Neoverse V3 core IP.
Starting with the core, the Arm Neoverse V3 core is Arm’s high-performance “V” series core design. A common example of a customer who uses the Neoverse V series is AWS, which started using the Neoverse V1 cores in Graviton3. The latest AWS offering, Graviton5, uses Neoverse V3 cores as well.
That core is then one of many and also needs access to PCIe I/O, accelerators, memory, and so forth. As a result, the Arm CMN-S3 underpins the chip. CMN, in Arm parlance, stands for the Coherent Mesh Network, which is important when you want the core to work as part of a broader system. We are now roughly two decades removed from the last single-core server CPU launch, so when we talk about the additional work going from having a Neoverse core IP to a functioning chip, a lot of the work in modern CPUs is just getting all of the integrated parts to communicate efficiently.
Taking the Arm Neoverse V3 cores and the Arm CMN-S3 with supporting IP, we get the Arm Neoverse CSS V3. At that point, we have the base CPU IP, but we are still a long way from a physical product.
To make the Arm AGI CPU, Arm needed to build out the entire chiplet on TSMC N3P, and then tie two of those chiplets together.
We went into a deeper dive as part of our Arm AGI Data Center CPU at Hot Chips 2026 coverage, but here are the main speeds and feeds from that presentation.
The bottom of that table includes some important but often overlooked parts of server CPU design. Server CPUs have more than just high-speed PCIe and DDR interfaces these days. For example, modern chips need communication channels for the BMC and sensors. Also, features like RAS and power and thermal management really get set when you build a physical chip.
Once you have a physical chip, there is still a lot more ground to cover, because you need to see if it works.
Once you have a physical chip, there is still a lot more ground to cover, because you need to see if it works.
