A few months back AMD launched their EPYC 8005 “Sorano” family of server chips. The mainstream server counterpart to AMD’s high-end EPYC 9005 chips, Sorano filled a significant hole in AMD’s chip lineup by bringing their Zen 5 architecture to a more modest server platform.
As we noted in our review at the time of the launch, Sorano has become a rather significant offering for AMD not only because of the market it fills, but because of just how much it has improved over its own predecessor, the Zen 4-based EPYC 8004 Siena. With a larger number of cores, far higher clockspeeds, and support for much faster DDR5 memory, Sorano made AMD’s SP6 platform a far more capable and competitive offering in the market.
A consequence of that, however, is that almost everything that customers knew about the 8000 series went out the window; despite using the same socket, the Sorano chip family is significantly different in terms of everything from performance and price to the number of individual SKUs within the chip stack. So what are the highlights among the EPYC 8005 family, and what chips should customers go with? To answer that, here is ServeTheHome’s look at the EPYC 8005 product stack, outlining what some of the best options for different scenarios/optimization points.
AMD EPYC 8005 SKU List and Value Analysis
First up, here is the complete list of EPYC 8005 chip SKUs.
For their first generation of 8000 series parts, the EPYC 8004 Siena, AMD kept things relatively simple with a modest product stack and consistent features among all of the chips, and that is once again the case for Sorano. The mid-tier, single-socket server platform does not gate any features behind specific SKUs, and as a result every chip from the entry-level 8 core 8025P to the top-end 8635P gets access to same set of features. This includes 6 channels of DDR5 memory support (including 2DPC support), 96 PCIe Gen5 lanes, and, of course, AMD’s Zen 5 CPU architecture. With Sorano being a notable step up here since these are AMD’s higher-clocking full-size Zen 5 cores, and not the compact cores used in Siena.
For potential customers, this simplifies the calculus behind picking which chip to go with by quite a bit. The only real decisions to be made are around core counts, power consumption, and all of the second-order effects thereof. Drop-in upgrades are even a viable option here since AMD is using the same SP6 socket as with the EPYC 8004 generation – though as we have seen, some vendors are releasing new motherboards for Sorano anyhow.
Even with just 7 chip SKUs, however, the spread between them in core count, clockspeeds, and power consumption are significant. The SP6 IOD can be connected to up to 12 Zen 5 CCDs, so AMD has run the gamut here, with between 8 and 84 CPU cores. This means that while they all share the same platform and architecture, the resulting performance of these chips can be quite different depending on the workload. All of which makes understanding and profiling a target workload all the more important in choosing a chip.
One important factor is going to be how well a workload scales up over multiple cores, versus requiring faster individual cores to hit its best performance. Every single chip SKU has a maximum single core turbo clockspeed of 4.5GHz (a significant improvement from EPYC 8004), so very lightly threaded workloads have a lot of headroom. But, generally speaking, one is not buying an EPYC CPU just to run a couple of threads. Rather, there is some major scale needed here in terms of core counts, I/O lanes, memory bandwidth – or possibly all three.
Taking a look at all-core turbo clockspeeds, we see that clockspeeds here are almost, but not entirely, inverted with core counts. The 84 core EPYC 8635P offers an all-core turbo boost speed of just 3.45GHz, while the 24 core 8225P hit 4.1GHz, and the smallest 8025P can go higher still. The outlier that breaks this pattern is the 16 core 8125P, which despite having fewer cores than the 8225P actually has a lower all core turbo clockspeed.
Outside of the 8125P, no single chip here is quite the sweet spot for per-core performance. But the middle-child 8325P has the strongest claim.
Shifting over to power consumption, AMD’s default TDPs are directly proportional to the core counts, even with the lower core chips offering higher average clockspeeds. For “performance at all costs” there is the 8635P with its 84 cores and 225 Watt TDP. With 20 more cores than the next-fastest chip it is the clear winner in terms of throughput. And, somewhat surprisingly, it is a lot more power efficient than the next chip down as well; the cost of going from a 64 core chip to an 84 core chip is just 15 Watts at default TDPs. AMD’s default TDPs vary from chip to chip, but in general the higher-end Sorano chips are all relatively close to each other in TDP at around 200 Watts – thanks in part to those higher clockspeeds we talked about earlier.
This also means that there is a clear and consistent progression from one part to the next in regards to how much power is needed per core – and really, the overall energy efficiency of the chip. The top-end 8635P ends up being the most efficient, at just 2.7 Watts per CPU core. This rises to a bit over 4.1W with the 48 core part, and finally to nearly 12W per core with the 8 core 8025P. With the entire EPYC 8005 family sharing the same IOD with the same memory and PCIe support, this is a classic case of where the power costs of the uncore (or IOD, in this case) are getting amortized over fewer and fewer CPU cores as the overall core counts drop down.
The flip side to that general decline in per-core energy efficiency is that fewer cores to amortize the impact of the IOD also means that there are fewer cores sharing/competing for other uncore resources, which can be beneficial in other ways. A prime example is the amount of L3 cache per core, which generally increases as the CPU core counts decrease. This is chiefly due to how AMD goes about building these SKUs and the number of CCDs they use, with most SKUs utilizing CCDs with multiple disabled cores – leaving more cache for the rest of the cores.
With 384MB of L3 cache, the top-end 8635P is, of course, the most cache-filled chip. But with so many cores, it also works out to be tighter on cache per core than most, at just under 4.6MB per core. Though it is the 64 core 8535P that is actually the most cache-contested chip here, at just 4MB per core thanks to AMD using 8 fully-enabled CCDs. Fittingly, the smaller core count chips have the most cache per core overall; the 8435P and 8225P both have 5.3MB per core, while the remaining three SKUs all get a spacious 8MB of cache per core.
Especially with AMD not producing 3D V-Cache server part in this generation, this makes the 8325P and its ilk one of the best options for highly-threaded workloads that strongly benefit from additional L3 cache.
As for overall memory bandwidth, with all seven 8005 chip SKUs sharing the same 6 channel DDR5-6400 memory controller, the amount of memory bandwidth on the SP6 platform is fixed. Or to put it another way, the amount of bandwidth per core is directly (and inversely) proportional to the core count. With 307GB/second of memory bandwidth overall for the platform, the 8 cores on the 8025P get an ample 38GB/second each; while at the top end the 8635P reduces that to just 3.7GB/second per core.
Finally, how does all of this look with pricing taken into account?
As AMD’s more budget-friendly server platform, SP6 and Serano is fairly cheap as far as server chips go. In practice, almost all server builds are going to spend more on RAM to fill the server than they will the CPU itself. With the caveat that nearly no one pays AMD’s list prices for their server CPUs, AMD’s chip pricing is somewhat variable; lower SKUs are always cheaper, but they do not scale consistently with price. Which means the price-per-core bobs up and down from one SKU to the next.
The best value here is found in the 16 and 24 core SKUs, which at list price are under $50 per core. In relative figures, it is actually a pretty significant improvement over the other SKUs, which are $60+ per. Understandably, the 8 core SKU does not fare especially well here at $66 per core. Otherwise, the top-end 84 core SKU is actually decent for being a top chip, at $69 per core. The weakest SKU, interestingly enough, is the 64 core SKU, which is priced only a few hundred dollars less than the top-end chip, yet drops 20 cores in the process. As a result, it works out to being $86 per core – a significantly higher price than any of the other SKUs.
Final Words
As AMD’s more economical server platform, the EPYC 8005 Sorano family fills an important role in the company’s server lineup. With more than a few customers in need of a literally smaller chip family that can still bring the full advantage of the Zen 5 feature set but without quite so many CPU cores or expensive memory channels, the EPYC 8005 family fills that role well. And with AMD keeping the chip stack relatively simple at just 7 SKUs and without any major feature differentiators, it keeps the overall chip calculus for customers reasonably straightforward.
For pure compute throughput, the EPYC 8005 stack is rather clear-cut. The 8635P is easily the fastest chip in terms of total (on paper) compute throughput thanks to its 84 CPU cores, as well as looking very good in terms of power efficiency. The trade-off there is that clockspeeds are not all that high compared to other SKUs, and it has some of the highest contention for cache and memory resources. The smaller core count chips cannot push the same total throughput, but they can do have more cache and memory bandwidth available per core – and, depending on the specific SKU, often much higher clockspeeds as well. Overall, different SKUs excel in different metrics, so there is no one-size-fits-all recommendation across the entire stack, though the 32 core 8325P does tick a lot of boxes here as a potential jack-of-all-trades.
Still, all of this underscores the importance of understanding the workload that will be run on an EPYC 8005 server. Even with just 7 SKUs, the wide range in core counts (and fixed aspects elsewhere) means that optimizing for compute, for memory, and for cost all have different optimal point. For AMD it means the EPUC 8005 lineup can serve a wide breadth of customers, but it means customers need to do their homework to figure out just what they need.
