AMD EPYC 7003 Date Set for Milan

Milan Milano Cover
Milan Milano Cover

AMD has finally announced a date for its next-gen processors codenamed “Milan”. We could simply tell you that it is on March 15. That was the plan. Then I got the cover image from our Editor-in-Chief who is a cookie aficionado. Instead of simply saying it is being launched on the “Ides of March” he sent me this last night as the way he is remembering (other than preparing our launch coverage.)

Milan Milano
The “Milan Milano” Click for larger version

AMD may or may not have been working with Pepperidge Farm for many years to message when the next-gen server processors will be launched. Please note, based on this the Dark Chocolate version seems to reference an EPYC 8000 series.

All “Milan Milano” fun aside, there is not much to the press release, but we have a rule of not just re-posting press releases without some sort of value-add. Here, admittedly our value add is a little fun.

Excerpt From the Press Release

AMD will host a digital global launch of the new 3rd Gen AMD¬†EPYC™¬†processors on Monday, March 15, 2021 at 8 a.m. PT / 11 a.m. ET.

The digital launch is slated to feature presentations by AMD President and CEO Dr. Lisa Su, Executive Vice President of Technology and Engineering and CTO Mark Papermaster, Senior Vice President and General Manager, Datacenter and Embedded Solutions Business Group, Forrest Norrod, Senior Vice President and General Manager, Server Business Unit, Dan McNamara and appearances by industry-leading data center partners and customers.

The launch will be accessible on the 3rd Gen AMD EPYC launch site starting at 8 a.m. PT/11 a.m. ET. A replay of the webcast can be accessed after the conclusion of the live stream event and will be available for one year after the event. (Source: AMD)

Final Words

You can check out the 3rd Gen AMD EPYC launch site which will host the event. Better yet (or in addition) you can check STH for our coverage as soon as we can post it. We were specifically asked not to post anything in this coverage, so you get the “Milan Milano.”

We cannot go into detail about AMD EPYC Milan, nor the upcoming Intel Ice Lake Xeons. As always though, we will bring information to our readers as we are allowed to.


  1. I guess INTEL is going to make a “big” announcement on the 14th :-)

    In fact, it is already written in the “signs” which the wise people who can see:

    March = 3, 14, 15 which means 3.1415…

  2. Does this mean that we’ll finally get the Milan reviews that STH has been sitting on for months?

  3. What did I see on STH? This is great creativity. A lite article on information, but if you wanted to get us to remember a date, I’d say high effectiveness.

  4. On March 15th EPYC Milan will be immediateli available also on DELL, HP, Lenovo, etc servers ? Or we will have to wait more?

  5. Defenetley worth waiting,
    i’m curious about STH opinion ;)

    processor : 254
    vendor_id : AuthenticAMD
    cpu family : 25
    model : 1
    model name : AMD EPYC 7713 64-Core Processor
    stepping : 1
    cpu MHz : 2000.000
    cache size : 512 KB
    physical id : 1
    siblings : 127
    core id : 125
    cpu cores : 64
    apicid : 253
    initial apicid : 253
    fpu : yes
    fpu_exception : yes
    cpuid level : 16
    wp : yes
    flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc art rep_good nopl nonstop_tsc extd_apicid aperfmperf eagerfpu pni pclmulqdq monitor ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_l2 arat cpb hw_pstate npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local
    bogomips : 3992.91
    TLB size : 2560 4K pages
    clflush size : 64
    cache_alignment : 64
    address sizes : 48 bits physical, 48 bits virtual
    power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14]


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