3rd Generation Intel Xeon Scalable “Cooper Lake” Processor Overview
The new 3rd Generation Intel Xeon Scalable platforms have a number of key improvements but also areas that are still the same versus the previous generation of 2nd Gen Intel Xeon Scalable processors.
As a quick note, the Purley platform (Skylake/ Cascade Lake) socket is Socket P or LGA3647. This shared a pin count but ultimately not the same socket with Xeon Phi x200. The new Cooper Lake / Cedar Island platform uses Socket P+. Socket P+ is a 4189 pin socket to handle extra I/O from the processor.
Since the way we are going to explain Cooper Lake is in the context of Cascade Lake (and Refresh) Xeons, let us start with the cores.
3rd Generation Xeon Scalable Core Update
With Cooper Lake, we get 28 cores maximum and the same 1.375MB L3 cache per core as we saw on 2017 Skylake and 2019/ 2020 Cascade Lake Xeons. The biggest jump perhaps is the move to a 250W maximum TDP. That means Intel can add new features but also it can keep higher sustained frequencies so long as the cooling solution is capable. A 45W TDP jump is massive and means that these will lead in performance per core at high core counts until updated Ice Lake cores and even higher TDPs are launched.
The cores themselves are fairly similar to the Cascade Lake cores as we understand, except for a few differences. Perhaps the biggest is support for bfloat16.
The key with bfloat16 is that it increases effective floating-point performance by retaining enough precision using half of the data of FP32. Since we have half the data, it also means more data fits in caches and memory which helps performance.
While Intel has a growing portfolio of other AI technologies including Intel Stratix 10 and future Agilex Next-Gen FPGAs, GPUs, Habana Labs chips, Movidius, and others, the idea is to enable deep learning training using unused CPU cycles that customers already have in their environments. Intel offers that it is less expensive to use CPUs that you already own versus buy GPUs specifically for deep learning. One also can benefit from CPU features such as large memory footprints. Of course, Intel on the briefing for the 3rd Gen Xeon Scalable offered a new Stratix 10 NX FPGA (note this is not 10nm Agilex) to further the idea that it is pushing a portfolio approach:
With Cooper Lake, we still get VNNI support for Intels cross-segment inferencing acceleration as well as AVX-512 with dual-port FMA.
Intel did not say this in the briefing, but a fairly valid way to think about a Cooper Lake chip is that it is like Cascade Lake chip with higher TDP, some memory controller tweaks, float16 added, and more UPI links. There are a few other differences, but realistically, the delta between the 2nd and 3rd generations of Xeon Scalable are not as big as we will start to see later this year with Ice Lake Xeons.
3rd Generation Xeon Scalable SKUs
We are going to have our formal SKU and value analysis, but here is Intel’s chart on the new SKUs:
There are 11 SKUs being launched today. We expect Intel to plug some of the holes in this lineup with additional SKUs over the next few months.
Here is what that looks like with some of the basic metrics:
Overall, these chips are in-line with the 2019 generation of Cascade Lake parts. We do not see severely out-of-step pricing since the market would likely not bear something like a Xeon Gold 5318H at $10000 and going up from there in the line. Competition is a good thing.
More on this in a separate piece.
Next, let us start looking at the platform components.