As part of the company’s Supercomputing 2018, a new FPGA accelerator card was announced by Xilinx. The Xilinx Alveo U280 is one of the company’s pre-ACAP 16nm UltraScale+ architecture FPGA products. The U280 features 8GB of Samsung High Bandwidth Memory (HBM2) plus 32GB of DDR4 memory. The goal of the new card is to accelerate database search and analytics, machine learning inference, and other memory-bound applications.
Xilinx Alveo U280 Supports ARM and AMD CCIX
Buried in the documentation for the card is a nugget of extremely interesting information:
The U280 acceleration card includes CCIX support to leverage existing server interconnect infrastructure for high bandwidth, low latency cache coherent shared memory access with CCIX enabled processors including Arm and AMD. (Source: Xilinx Alveo U280 whitepaper WP50 (v1.0) accessed 16 November 2018)
We were recently at the AMD Next Horizon Event and STH friend Dr. Ian Dr. Ian Cutress at Anandtech (not a typo, that is what his SC18 badge said) touched upon this in his interview with AMD CTO Mark Papermaster. Neither in the Rome disclosure nor the interview did AMD confirm CCIX support. However, AMD publicly supports CCIX and Gen-Z and when we asked if this means Rome supports CCIX all we received was that AMD supports CCIX but has not announced a product with it yet. Arm may have chips derived from its IP with CCIX support, but AMD has a more well-defined roadmap.
What then could this AMD CCIX enabled processor be so that the Xilinx Alveo U280 claims to support? Xilinx may be referring to “Milan” the generation after Rome, but given Rome is the next major release, and AMD has the opportunity with the IO hub to change the game, x86 CCIX support is possible as early as 2019. Announcing a Xilinx Alveo U280 card in 2018 that will ship in Q1 2019 with CCIX support for AMD’s Milan seems less likely than the 2019 AMD “Rome” generation of AMD EPYC. If there was no AMD processor on the immediate roadmap with CCIX support, then it would indeed be a strange addition stating support in the product documentation.
This slip is a big deal. If AMD indeed is enabling CCIX support, it will have a coherent interconnect that can bring accelerators such as the Xilinx Alveo U280 onboard using something other than vanilla PCIe Gen4. We think the line above is significant since Xilinx is not highlighting PCIe 4.0 support for the Alveo U280 and AMD EPYC Rome even though that has been announced. As a quick aside, if you were going to do the first generation CCIX or Gen-Z enabled platform, moving to a dedicated I/O die might be a good first step.
Xilinx Alveo U280 Key Specs
Here are the Xilinx Alveo U280 key specs for those who want a high memory bandwidth FPGA:
|Card Specifications||Xilinx Alveo U280|
|Passive Cooling Option||Active Cooling Option|
|INT8 TOPs (peak)||24.5||24.5|
|Width||Dual Slot||Dual Slot|
|Form Factor||Full Height, 3/4 Length||Full Height, Full Length|
|HBM2 Total Capacity||8GB||8GB|
|HBM2 Total Bandwidth||460GB/s||460GB/s|
|DDR Format||2x 16GB 72b DIMM DDR4||2x 16GB 72b DIMM DDR4|
|DDR Memory Capacity||32GB||32GB|
|DDR Total Bandwidth||38GB/s||38GB/s|
|Internal SRAM Capacity||41MB||41MB|
|Internal SRAM Total Bandwidth||30TB/s||30TB/s|
|PCI Express||Gen4x8 with CCIX||Gen4x8 with CCIX|
|Network Interfaces||2x QSFP28 (100GbE)||2x QSFP28 (100GbE)|
|Look-up Tables (LUTs)||1,079,000||1,079,000|
|Power and Thermal|
|Maximum Total Power||225W||225W|
The Xilinx Alveo U280 is surely an interesting solution. It clearly shows that Xilinx is committed to a roadmap of products in the Alveo line, and we eagerly await the arrival of a Versal version.
If indeed this is a slip announcing AMD CCIX support for the Xilinx Alveo U280, that is a huge deal. When we talk to folks in the industry, CCIX and Gen-Z are undoubtedly where this is going. Dell EMC announced Alveo support at SC18 and it is fairly clear that the “WowerEdge” Dell EMC PowerEdge MX is built for Gen-Z support in a few years. If AMD and Xilinx announce CCIX support in 2019, that is going to kickstart the entire server ecosystem and Intel will be forced to respond.