Xilinx ACAP Hot Chips 30 Keynote with Victor Peng

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Victor Peng Keynote Hot Chips 30
Victor Peng Keynote Hot Chips 30

At Hot Chips 30, the CEO of Xilinx, Victor Peng, gave an awesome keynote about the company’s vision. We are going to take some notes of the live presentation here. The page will refresh every few minutes with more information.

Xilinx and Pervasive Intelligence Background

The keynote started with a nod towards the idea of pervasive intelligence. Everywhere that there are machines or sensors, we are seeing more intelligence.

Xilinx Pervasive Intelligence
Xilinx Pervasive Intelligence

Hyperscale data centers are growing as a percentage of overall data center spend. The growth in data and market caps show that there is an opportunity.

Xilinx HC30 Growth Trends
Xilinx HC30 Growth Trends

Moore’s law and Dennard scaling are slowing down, creating challenges meeting the computation needs of the data being generated and intelligence required.

Xilinx HC30 Saling Challenges
Xilinx HC30 Saling Challenges

A key challenge is the power density growth. Power is seen as the main limiter toward next-generation applications. We can build more chips, but not power efficient enough.

Xilinx HC30 Power And Density Growth
Xilinx HC30 Power And Density Growth

One of the new waves is domain specific architectures on hardware that can adapt to different workloads. This includes CPUs, GPUs, and FPGAs.

Xilinx HC30 Domain Specific Hardware
Xilinx HC30 Domain Specific Hardware

Victor Peng’s anecdote is that the most adaptable species wins in evolution. That is part of the Xilinx ACAP program.

Xilinx HC30 Scale Out Requires DSAs And Adaptable Platforms
Xilinx HC30 Scale Out Requires DSAs And Adaptable Platforms

Automobiles of the future want over the air updates.

Xilinx HC30 Auto Update
Xilinx HC30 Auto Update

How Xilinx is Addressing the Market

Application acceleration can happen with FPGAs at the speed of software updates, rather than hardware spins.

Xilinx HC30 Application Acceleration With DSAs On FPGA
Xilinx HC30 Application Acceleration With DSAs On FPGA

Development for data centers means that the company is part of a large ecosystem enabling the next-generation of intelligence.

Xilinx HC30 Development For Domains
Xilinx HC30 Development For Domains

The company is working with applications and machine learning developers to help software developers use FPGAs at a lower power and higher performance.

Xilinx HC30 Stack For ML Acceleration On Xilinx
Xilinx HC30 Stack For ML Acceleration On Xilinx

Xilinx ACAP Performance

The performance of the solutions can be better than GPUs. Using AWS instances, for latency-sensitive high-resolution imaging.

Xilinx FPGA Acceleration V GPU Imaging
Xilinx FPGA Acceleration V GPU Imaging

It can also help in cases of security and anomaly detection.

Xilinx FPGA Anomaly Detection
Xilinx FPGA Anomaly Detection

For smart cities, and security, Xilinx is showing image recognition, transcoding and tagging workloads on their architecture.

Xilinx FPGA Smart City Security
Xilinx FPGA Smart City Security

Xilinx ACAP Programmable Architecture Milestones

Now the keynote is following the progression of the FPGA. Current generations have more processors with ZYNQ FPGAs.

Xilinx Programmable Architecture Milestones
Xilinx Programmable Architecture Milestones

ACAP is the future. Adaptive Compute Acceleration Platform is being released next. We discussed this first in our Xilinx Project Everest and ACAP Strategy at 7nm.

Xilinx FPGA To ACAP
Xilinx FPGA To ACAP

ACAP is a modular architecture. Not every chip will have HBM onboard.

Xilinx ACAP Areas
Xilinx ACAP Areas

ACAP will be used from automotive to data center. It is not just an FPGA.

Xilinx ACAP Performance Generation Over Generation
Xilinx ACAP Performance Generation Over Generation

Performance gains generation on generation is significant, up to 20x.

The new tool suite will do the placement and other aspects to leverage hardware so you do not have to be a FPGA programmer to use ACAP. Xilinx is making a major investment in software.

Xilinx ACAP HW And SW Programmable Architecture
Xilinx ACAP HW And SW Programmable Architecture

TOPS are becoming the new megahertz wars from the 1990’s. The ACAP is getting performance gains at a few hundred megahertz to a gigahertz. There is a massive amount of on-chip bandwidth.

Xilinx ACAP XDNN
Xilinx ACAP XDNN

Xilinx recently announced the intent to purchase DeePhi. DeePhi has architectures for machine learning.

Xilinx ACAP Soft Overlay Architectures For ML
Xilinx ACAP Soft Overlay Architectures For ML

Final Words

At STH we will be covering the Xilinx ACAP as it is released. Stay tuned for more information. The company is heading in the right direction here. One of the biggest obstacles to adoption of FPGAs in the AI markets is programming. Building toolsets to allow the benefits of ACAP acceleration without having to know RTL is the right way to address this market.

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Patrick has been running STH since 2009 and covers a wide variety of SME, SMB, and SOHO IT topics. Patrick is a consultant in the technology industry and has worked with numerous large hardware and storage vendors in the Silicon Valley. The goal of STH is simply to help users find some information about server, storage and networking, building blocks. If you have any helpful information please feel free to post on the forums.

1 COMMENT

  1. Long time reader… I’m real excited about all the options coming, especially for EPYC… I do feel that they are overlooking HSA coherency though in APUs… But then AMD could create a DS SoC using Jaguar since it’s SW programmable arch… Then there’s the guts of shaders combined with FMAC FP in EPYC and many levels in between…

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