At OCP Summit 2025, we had the opportunity to see the newest Broadcom switch chips straight out of a briefcase. What was striking about the new Broadcom Tomahawk 6 102.4T switch chips was not just their size and construction, but also the difference in package sizes due to the different SerDes speeds. As a bonus, a Tomahawk Ultra also emerged from the same briefcase.
Broadcom Tomahawk 6 102.4T Switch Chips and Tomahawk Ultra
Both of the packages you see below are Tomahawk 6. At OCP Summit 2025, we were able to see two of the packages. On the left, we have the 112G SerDes part, and on the right, we have the 224G SerDes version.
The 112G SerDes version needs more I/O lanes, so the package is much larger.
In contrast, the 224G SerDes version needs fewer lanes since they are running at higher speeds, making the package smaller.
As a bonus, we were able to see the Tomahawk Ultra 51.2T switch chip. This package was considerably smaller.
Also worth noting that we can see the Tomahawk 6 chiplets/ tiles very clearly in the shots above, but the Tomahawk Ultra design is very different.
We had some folks ask if the Tomahawk Ultra was just a Tomahawk 6 running at half speed. From these photos, you can see that the actual silicon packages are very different.
Final Words
It is always neat to see the new chips. Usually, these are buried under either large heatsinks or liquid coolers. Getting to see the Tomahawk packages pulled from a briefcase and placed onto a ledge in a Marriott during OCP Summit 2025 is always a great opportunity to bring our STH community these new chips. It also shows just how much goes into these different designs. Broadcom is on a mission to scale Ethernet everywhere, and these along with the Broadcom Thor Ultra 800GbE NICs are designed for next-gen high-performance compute clusters.
It’s hard to judge the scale from photos like that. Putting some reference like a coin next to them would help.
Wow, really cool. Would have liked to have been able to see the pad arrays and the pin counts in addition to these photos. Also, I agree with @Kyle, a size reference like an LGA-4677 Xeon or a Socket SP3 or SP5 Epyc for scale would have been nice.
Slight typo with “Tomhawk”
Though obviously not approaching coaster-size (I recognize the crystals in that countertop), a banana would have been helpful for context ;)
12.8 terabytes per second of data processing throughput is absolutely mad.