What would we call disaggregation of a SoC (System-on-Chip) disaggregation to something more akin to a SoP (System-on-Package) approach? We are going to use SoC Containerization to communicate the concept here. As part of Intel Architecture Day 2020, Intel showed a number of technical advancements. There was a very short portion of the presentation dedicated to its future SoC and IP methodology which has some stark potential to change the way Intel presents itself in the market.
“SoC Containerization” Future Methodology
Packaging sounds abstract, but if you look at what Intel is doing today, there are a few dies being integrated. Intel is looking well beyond doing a handful of dies such as with Lakefield. Instead, the company is moving from monolithic dies to multiple dies and eventually to individual IP blocks.
Of particular note, Intel here has the GPU, CPU, and IO die separately illustrated. That looks a lot more like an AMD model of disaggregation. It also makes a lot of sense since we would likely have either PCIe Gen4 or Ice Lake Xeon cores today if Intel had moved to I/O die and disaggregation in this generation. The individual IPs are where this gets fascinating. Here is an illustration:
This has huge applications beyond the client space. For example, what if Intel on the Xeon side had four versions of the Xeon Gold 6520 (fictional part)? There could be a:
- Xeon Gold 6520A – ASPEED BMC
- Xeon Gold 6520D – Dell iDRAC BMC
- Xeon Gold 6520H – HPE iLO BMC
- Xeon Gold 6520L – Lenovo XClarity Controller BMC
- Xeon Gold 6520G – Google Custom BMC
That would mean that the Xeon you buy from Dell would be different than Supermicro or HPE. Incidentally, integrating an ASPEED BMC would have a fairly significant server motherboard area reclamation impact especially if DRAM and NAND chips could be stacked and integrated.
One way to productize this is that Intel could define the IP blocks. For example, Intel could have a media codec block that was different for a future Core i9 than a future Core i3 and that could be the same across different IP blocks.
The other way this could be productized is to allow OEMs and customers to define chiplets used and therefore products. Dell could have a Intel Core iDell-1370 that uses different IP blocks than an Intel Core iHP-1370.
Could one put a Core iHP into a Dell system and should that work? If not, then we are going down a path of limited hardware recyclability which is not an eco-friendly approach. If it does work, then does Quanta make the notebook and HP or Dell’s value-add become less about the mechanical design and more about the SoC design and distribution chain? What if the Dell server part has a specific VMware optimization and vSphere license tied to the actual chip IP block? There is a ton to unpack with this model.
I asked Raja about this strategy, and he referred me to the presentation since he did not want to make a new disclosure.
What I will say is that if this is truly Intel’s direction, then defining this strategy and building the chiplet ecosystem could be, by far, the most important job at the company. If you look at PC’s from pre-2000 they were cobbled together with IP blocks represented by ISA, PCI, accelerator socket, and even modular cache slots. Over time, the GPU moved to the SoC. The audio went from being an add-in card to being a small motherboard chip. The same happened to network connectivity. In the future, audio and networking could move to a chiplet making for a true SoC (or SoP.) Today’s motherboards effectively become tomorrow’s SoPs.
True disaggregation to chiplet IP blocks is what we are going to call “SoC Containerization.” Instead of a monolithic software application or hardware SoC, one gets a solution built of lower-level components. These lower-level components can be iterated on at different rates, much like a container-based software application.