Samsung has new 12nm-class DDR5 DRAM. This is a big deal in the industry for several reasons. DDR5 is the new generation of DRAM, replacing DDR4, that is powering new generations of servers and desktops. We have already looked at desktop platforms as well as the AMD EPYC 9004 “Genoa” series that utilize DDR5, and have used DDR5 in the upcoming Intel Xeon series codenamed “Sapphire Rapids.” Samsung’s announcement is a big deal.
Samsung Introduces 12nm-Class DDR5 DRAM
Samsung says its 16Gb (gigabit) DDR5 DRAM is the industry’s first 12nm-class process DDR5. Process in the DRAM industry helps shrink the amount of die area required to achieve a given bit density. As a result, the new DRAM is expected to use less power and eventually be less costly than earlier DDR5 revisions.
Samsung says producing 12nm class memory required new high-k material increasing cell capacitance along with extreme ultraviolet (EUV) lithography, and other technologies. The net impact is that Samsung says that its new memory “will help unlock speeds of up to 7.2 gigabits per second (Gbps.)” (Source: Samsung)
As part of the announcement, Samsung also said that it had completed compatibility work with AMD, and we would expect work with Intel is underway. AMD’s quote in Samsung’s press release was from its client business not the data center side.
At STH, we generally use ~5W as a figure for a current-gen DDR5 RDIMM. That means in an AMD EPYC Genoa server like the Gigabyte 2P AMD EPYC Genoa GPU Server from SC22 we might expect ~240W of power draw from the 48x DDR5 RDIMMs (when Genoa supports 2P 2DPC.) Or to put it differently, modern DDR5 power draw is set to be more than the two processors, combined, found in 10-year-old high-end Intel Xeon E5 servers.
The bigger question is reliability. As storage has moved from rotating hard disks to NAND flash and SSDs, this is an increasing concern in servers. The industry has seen increasing reliability challenges with smaller lithography DRAM, and with many servers not using hard dives, plus the sheer number of DIMMs in systems, memory reliability has become a bigger concern. Hopefully, the new Samsung 12nm-class DDR5 proves not just to be faster, cheaper, and with lower power consumption, but also with higher reliability.
“The industry has seen increasing reliability challenges with smaller lithography DRAM”
I can attest to that. Even with my fairly small datacenter sample size, the random DDR4 failure rate has been…alarming.
Initial experience with DDR5 on the desktop side hasn’t given me any reason to be optimistic.
Why do you keep mechanically repeating the blurbs without any critical response ?
What does “increased cell capacitance” have to do with transfer speeds ?
For this to be legit news article, one would have to know where the tech was before this transition.
Fine, they used EUV instead of DUV, but AFAIK this was conditioned by process change ( DUV is economic choice up to 14-ish nm IIRC), not anything special that Samsung for this product.
Needs a “Press Release” tag.
>What does “increased cell capacitance” have to do with transfer speeds ?
More capacitance means less time wasted refreshing.
The 50th anniversary of the first practical DRAM, the Mostek MK4096, is approaching.
It might be worthwhile to post a historical timeline article, showing the progress (or lack thereof) on key DRAM metrics.
No one will be surprised by the charts for dollars-per-MB by year (X-axis) and server RAM bandwidth by year, both of which are apt to need logarithmic Y-axes.
Watts-per-MB trend could be interesting.
Latency progress (as first-byte-out nS, not CAS counts) might be depressing.