Intel recently posted an article outlining the ECC schemes found in its Ethernet controllers. For those that do not know, Intel Ethernet controllers have small (tens of KB usually) send/ receive buffers that help performance but are another point in the memory chain. After posting the RAID Reliability Anthology Part 1 I was contacted by a few folks that are fairly regular IEEE publishers on the subject for the big enterprise storage firms. One point that came up a few times is that using a triple parity scheme, such as RAID-Z3 would likely not be best modeled by a Poisson MTTDL distribution because at that point one is more likely to see failures of other hardware components such as RAID cards, Fiber Channel/ Ethernet controllers, DRAM and etc. Since that series of sit downs, I have been keeping an eye on other components a bit more closely.
The above table that I got the data from in this Intel post, shows a few interesting things. First, the almost de-facto onboard Intel controller utilized by many motherboard manufacturers, the Intel 82574L is relatively rudimentary. The lack of ECC there is not a big issue for things like a management NIC for VMware ESXi 5.0/ VSphereNext, I recently did a piece on a six port Gigabit Ethernet controller, the Dell/ Silicom PEG6I that utilizes the Intel 82571 controller which fares better in terms of ECC. One other note is that the newer Intel I350 and X540 controllers both manage to have ECC. The Intel I350 is being used extensively (both in dual and quad port configurations) onboard newer dual socket LGA 2011 Xeon E5 platforms so that is a positive trend.
As for the impact of this, likely for the SMB and home segments, this is probably more of a nice to have feature that will provide another link in the overall error detection and correction chain. For larger enterprises, it may be worth ensuring one is using the newer generation controllers.