Unanswered Questions: Thermals, Costs, & Customers
With everything that IBM is announcing today it has raised a lot of hope for the future of silicon chip manufacturing, but it has also left quite a few unanswered questions on both the technology front and the business front. These are things that IBM is already addressing in some form or another, but are aspects they are not going to answer until the nanostack technology is closer to production.
From a technical perspective, the biggest outstanding question is how to manage thermals. One of the many reasons that 3D transistor stacking has not been used so far is because it means placing a relatively hot transistor on top of another relatively hot transistor, which prevents traditional cooling methods from making contact with both transistors to cool them. Complicating matters, because each transistor can be (and almost assuredly will be) made from different materials, this means that the bonded wafers will likely have different coefficients of expansion – and then there is the bonding dielectric to worry about, as well.
The next big technical question is around yields and cost. Which is largely a proxy question for how well the bonding process works. Can wafers be bonded reliably enough to allow for yields similar to contemporary monolithic chips? This is a problem that chip stacking techniques already deal with today, and the margins on wafer stacking are much shorter.
And assuming this can be achieved at an acceptable yield, what is the cost per transistor going to be? After falling precipitously for decades, further reductions in the cost per transistor are already starting to flatten out. If IBM’s nanostack technology can fab chips with twice the density – and consume twice as many wafers in the process – can those chips be made at something meaningfully less than twice the cost?
Finally, on the business side of matters, who will IBM’s customers be? The company no longer uses its transistor research technology in-house, having sold off its fabs to GlobalFoundries in 2015. In recent years, Japanese upstart Rapidus has been IBM’s prime customer, licensing their 2nm GAAFET technology for their upcoming 2nm process node. But Rapidus is an unproven fab, to say the least, and whether they will be in a state to be able to license IBM’s nanostack technology is far from certain. That leaves the big three fabs – TSMC, Intel, and Samsung – all of whom are happy to license technology, but also have their own research teams and the option to license from other research groups as well. IBM is very unlikely to end up empty-handed here, but how much of the pie they can capture for technology licensing (and whether any of those customers will be publicly named) remains to be seen.
Final Words
It is a very rare day when a major new transistor design gets announced, so today is one of those very special days. IBM is promising nothing less than a paradigm shift with their nanostack transistor design, and understandably so. Reliably building transistors by stacking two wafers is a massive technical undertaking – and keeping them working is almost as large of a task. But the performance benefits are impossible to ignore: 50% area scaling and either 50% more performance or 70% less power would be an incredible improvement over contemporary GAAFET transistors.
Ultimately, some new form of transistor is going to have to succeed GAAFET in the next decade, and IBM believes that they have cracked the problem with their nanostacked transistors. There is still a long road to bringing these transistors out of the lab and into the fab, but if everything goes as well as IBM hopes, then we may be seeing chips based around their technology in as little as five years from now, in time for the 7Å generation of process nodes. At just three generations past today’s contemporary 2nm nodes, by modern chip fab technology standards that may as well be little more than a blink of an eye.
But regardless of the specific technology used, it is increasingly clear that the future of chipmaking must go 3D. With even GAAFET transistors likely to run out of headroom in a few years, and transistor sizes down to being measured in the tens of atoms, there is little room left to shrink transistors along normal 2D lines. Instead, with the prospect of nanostacking and then multistacking beyond that, the future for transistors is looking up – and in more ways than one.
