Walking the aisles at OCP Summit 2018 we stopped by the Ampere booth. In the booth, we saw the Ampere eMAG ARM server SoC in action. Despite the roots of this chip being the AppliedMicro X-Gene 3 which was shown off at last year’s summit, this year’s presence was much larger. In 2017, the Carlyle Group purchased the AppliedMicro X-Gene 3 assets from MACOM. They hired well-known industry executives and have been looking to take the next step. You can read more about the Ampere chip in our piece: Ampere 32 core 64-bit ARM Chip From X-Gene 3 IP. During the show we snagged some photos of the chip in action.
Ampere eMAG ARM CPU Photos
Ampere had chips floating around their booth encapsulated in acrylic stands. Given the San Jose Convention Center trade show lighting, this was challenging to capture to say the least. Here is the front of the chip from the show.
The flip side is easily more interesting. The pad array is not uniform across the bottom of the chip and there are many empty spaces. This is unlike what we see in most modern CPUs.
Beyond the chip itself, Ampere had the development system on display with a full set of 16x DDR4 DIMMs and three PCIe cards.
The development system was based on a Lenovo chassis which is why the layout may look familiar to many STH readers.
The Ampere team had demos of Intel Xeon Scalable CPUs compared to their CPUs and were able to show performance advantages. I asked when they would be shipping and it seems like they are scheduled to start shipping in some volume about when we would expect Cascade Lake based “early access” customers to start getting their systems. As a result, the Ampere solution was essentially shown as competitive as a single socket part addressing a part of the market that Intel does not currently have a great solution to address.
In terms of show floor visibility beyond the Ampere booth, Qualcomm Centriq 2400 had very little visibility but Ampere being a newer solution was very hard to find outside of the Ampere booth. Both Ampere and Qualcomm Centriq are essentially targeting a segment of the market for high performance single socket that Intel does not have a great solution for but it looks like the first generation products are going to be mostly used as lab demos rather than for broad deployments.
The Ampere 32 core 64-bit ARM Server CPU
Here is the key feature list of the solution:
- 32 Arm v8 64-bit CPU cores up to 3.3 GHz with Turbo
- 32 KB L1 I-cache, 32 KB L1 D-cache per core
- Shared 256 KB L2 cache per 2 cores
- 32 MB globally shared L3 cache
- 8x 72-bit DDR4-2667 channels with up to 16 DIMMs, 1 TB/socket
- Full interrupt virtualization
- I/O virtualization
- Enterprise server-class RAS
– End-to-end data poisoning
– Error containment and isolation
– Background L3 and DRAM scrubbing
- 42 lanes of PCIe Gen 3, with 8 controllers
– x16 or two x8/x4
– x16 or two x8/x4
– x8 or two x4
– Two x1
- 4 x SATA Gen 3 ports
- 2 x USB 2.0 ports
- TSMC 16 nm FinFET+
- 125W TDP
This is certainly a competitive part for the lower-end of the market. It is also yet another solution targeting 8-DIMMs per socket showing how Intel missed the mark with its six-channel DDR4 memory controller on the Intel Xeon Scalable line. Even this lower-end ARM CPU will address more memory than the current generation Xeon Scalable CPUs in a similar price / power segment.
For a quick reminder, the X-Gene 3 had 32 ARMv8-A 64-bit cores, 8x DDR4-2667 ECC memory channels supporting 2DPC (16 DIMMs) for a maximum of 1 TB RAM and 42x PCIe 3.0 lanes. Those types of specs, and ownership plays tell us that this is essentially a rebranded X-Gene 3 with the Ampere name.