AMD EPYC 8004 Siena SKUs and Pricing
Here is the SKU list for the AMD EPYC 8004 series. One can see a range from the 8-core AMD EPYC 8024P to the 8534P at 64 cores. For those wondering what the PN parts are, the N is for NEBS friendly which means things like a fixed TDP but a wider operating temperature range. For those wondering, “NEBS” is network equipment building system a common framework for telco systems. NEBS is a system-level certification so AMD can only say NEBS-friendly. It is interesting that AMD does not just have an E for embedded or something.
Here is the pricing. The AMD EPYC 8224P with 24 cores and the EPYC 8124P with 16 cores are really going to interest folks. If you have been looking at something Intel Core-level or Ryzen level, but want more PCIe Gen5 and ECC RDIMM memory, then this is going to be the option.
While we can thank AMD for only having 6 main SKUs plus 6 NEBS variants, and variable cTDP on the non-NEBS parts, the naming is still painful. The first digit is 8 and the last is 4 for Siena and 4th Gen EPYC. The P for the single socket is great. The middle two digits correspond to the number of cores and performance, but 32 cores and below in the EPYC 8004 is a 2 for performance and 48 and 64 cores are a 3.
While AMD’s SKU stack is much easier than Intel’s, Ampere still wins with the best SKU naming focusing on series, core count, and clock speed. Just for some sense, there is not a number in this naming convention for Zen 4 versus Zen 4c.
Final Words
This is a bit of a strange launch. We do not have benchmarks on day 1. It almost feels like AMD is launching just to get the news out ahead of Intel Innovation 2023 instead of just letting Siena have its time to shine. That is a bummer as this is an exciting product line. AMD needed something in the lower core count and power space, beyond the new Low Power AMD EPYC 7003 SKUs. This is what we have been waiting for over generations of EPYC.
What is really interesting is the strategy. AMD’s strategy is basically here are cores, DDR5 channels, and PCIe Gen5, go make something of it. Intel’s strategy for the telco edge involves things like Xeon D, Xeon EE, and more with onboard acceleration. This launch felt like an opportunity for AMD to show Siena along with former Xilinx Alveo cards to highlight the NEBS-friendly SKUs targeting the telco space.
The good news is that we will have reviews coming. A somewhat fortuitous alignment means that we are not doing launch day reviews the same week we have Intel Innovation 2023 and are moving the STH studio to a larger location. Siena might be the first new product line we do in the new studio.
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It’s the most wonderful time of the year. Upgrade season! Farewell Epyc 3000s, you did well. The boards supermicro made for you, not so much. Between these and whatever Intel debuts, looks like there will be some actual options for storage and firewalls when you don’t want or need a 200W+ CPU but still want the actual server goods without buying something in 2023 that still uses a C3000 atom. Maybe….maybe….new Intel Atoms next week as well?
Interesting! This fill out an obvious gap in the lineup between “low power/price” Milan and Epyc 9000.
With these new 16c Zen4c chiplets, the announcement lacks L3 cache size info on the different SKU’s, determining the number of chiplets on each of the variations.
Specs list 2 DPC operation, but is anyone implementing this, or is it missing like on the other Genoa platforms?
As shown by the Intel Max and AMD X series processors, on-package cache and memory makes a huge difference for w variety of workloads. From a marketing point of view I wouldn’t be surprised if the cache were half that of the regular performance cores; from an engineering point of view I’m hoping that’s not the case.
Since the original 32-core EPYC 7551 processors have the same 180w rating and are currently available new at closeout prices 18 times cheaper than the just announced 8324P, it would be interesting to see a head to head comparison between the two on a variety of workloads.
In general it’d be interesting to track performance over four generations of Zen processors. Since many of these systems are still available such a comparison could also be practical, especially when including these Zen 4c systems.
@Eric Olson,
The performance differences between Zen1 and Zen4 are fairly well documented. Look at the reviews they’ve done here and compare the values. Dual socket 7601 did 21 kernel compiles per hour, dual socket 9654 did about 105 kernel compiles per hour. 5x the performance with 3x the number of cores.
Its kind of weird that AMD is focusing on telco as the use case instead of the huge small business market. Most small businesses don’t need a Genoa based server and would prefer the 8-24 core sienna SKUs that are here but that isnt’ part of the target market for some reason.
¯\_(ツ)_/¯
> Genoa-X has a dirty open secret we are choosing to ignore
What’s that?
Wes V said “The performance differences between Zen1 and Zen4 are fairly well documented. Look at the reviews they’ve done here and compare the values.” That’s a good point. In the present announcement we are talking Zen 4c cores.
At any rate, since the core counts and power budgets are the same, I think a head to head comparison of the 7551 to the 8324P would be informative.
In reply to Anob, I think the secret is that Xeon Max works well for general computing even though the marketing claims it’s only good for HPC. I think a secret intended to mislead someone else is called a dirty secret, but not sure.