Since we covered many of the other talks, we also had a draft of the Infineon RISC-V for Automotive talk for Hot Chips 2026 ready. We figured, why not give this talk some exposure too? Let us get to it.
Infineon RISC-V for Automotive at Hot Chips 2026
Infineon opened with the compute demands facing automotive microcontrollers. Chassis, powertrain, and ADAS applications together want real-time low latency, power efficiency, and security on top of the highest integrity levels and functional safety, all on a single part.
Architecture work starts with the move from domain architecture toward zone control units and eventually full car computers. Former domain controllers evolve into central car computers handling ADAS, infotainment, and vehicle motion, while body and comfort functions consolidate into zones that share wiring and cut harness weight and cost. In automotive, the wiring harness is a huge deal.
Infineon lays out the real-time areas that every automotive part must handle. Fast control loops such as E-motor control need deadlines under 10 ms and interrupt latencies in the tens of nanoseconds, while strategic functions like vehicle management tolerate multiple seconds and 10 ms interrupt latency. We heard some of this in the Waymo Sensor Fusion Processor at Hot Chips 2026 talk.
With zone architecture in place, the open question is how much intelligence each zone controller should carry. Path A uses optimized multi-domain zone controllers that partially consolidate endpoint ECUs and support local power distribution, while Path B keeps zone controllers as low-complexity I/O aggregators with no intelligence of their own.
Infineon says that Option A is the more advantageous path. Keeping local tactics and latency-sensitive control loops in the zone while global strategies and OEM value sit in the central compute shrinks the vehicle attack surface, eases maintenance, and cuts system cost by consolidating endpoint ECUs and decentralizing power distribution.
Real zone controllers integrate workloads with very different compute demands. Real-time control, DSP and AI inference, low-power service layers, and audio processing all land on one part, so the compute architecture must scale across high-end multi-domain zones and low-end body zones while still delivering good power, performance, and area.
A super-integrated zone controller pushes heterogeneity further by adding an MPU island alongside the MCU. Offloading non-real-time critical workloads to a POSIX adaptive software stack frees the real-time core, enables faster boot and wake than a full SoC, and helps a zone scale from L2 toward L2+ and L3.
Against that backdrop, Infineon makes the case for RISC-V, which feels a bit like RISC-V over Arm given many of the other solutions out there. A single open and scalable ISA avoids IP-level lock-in, eases knowledge sharing, and brings ecosystem synergies across automotive, IoT, and industrial use.
Standardization depends on the right profiles. Within the RVI AUTO-SIG discussion, Infineon argues the distinction is less about auto versus non-auto and more about defining industry-grade safety- and security-related products, starting from a base such as RV32E and I plus M and U and adding optionalities for supervisor mode, floating point, vectors, and hypervisor support. If you want to learn more about profiles there was an Update on RISC-V Standards and Adoption at Hot Chips 2026.
Scalability depends as much on the software stack as on the ISA. Infineon points to virtualization as a key requirement so an RVM-based system can host multiple workloads and software domains cleanly.
RISC-V specifies the ISA rather than implementation details. Instruction latency, memory hierarchy, cache coherency, and functional safety features such as lock-step and error tracking stay in the hands of the silicon designer, which is where automotive differentiation happens.
Infineon says that in practice, detailed ISA aspects matter less than microarchitectural optimization, and for MCUs the winning attributes are memory, connectivity, specific hardware, sourcing, and final BOM cost, with the availability of automotive-qualified toolchains deciding who succeeds.
Infineon closes by tying RISC-V to concrete zone controller roles. RISC-V can accelerate zone control units, but application and cost fit are driven by factors beyond the ISA, such as SoC architecture, ecosystem enablement, and ease of deployment, and long-term adoption depends on standardized hardware-software interfaces and toolchain support.
That mix of open ISA freedom and the need for dependable, toolchain-backed automotive silicon frames where RISC-V fits as zone architectures mature.
Final Words
Infineon frames RISC-V as an ISA that removes the lock-in, but the market will be won on auto-qualified toolchains, SoC architecture, and ecosystem enablement rather than the instruction set alone. Hopefully, the automotive folks are able to support multiple ISAs unless one clearly pulls ahead. This was another neat talk, but probably one that was a bit less traditional STH coverage area focused.
