AMD is up first today on Day 2 at Hot Chips 2026 to walk through Versal Premium Gen2, its adaptive SoC platform for physical AI, data center, and mission-critical systems. We covered the family’s pivot from HBM to LPDDR5X memory on package when the parts launched.
This presentation is being done live, so please excuse typos.
AMD Versal Premium Gen2 at Hot Chips 2026
AMD says there are three pillars that must converge for edge devices: secure boot and crypto acceleration, secure high-speed interconnect and memory, and physical AI for low-latency environments.
This platform overview shows an FPGA-based adaptive SoC that pairs programmable logic with real-time application cores. AMD is explaining why they believe the platform is the best for physical AI and other applications.
AMD is now mapping the physical threats a physical AI system faces at the perimeter. Bus snooping, device substitution, tapped PCIe or DDR traces, and swapped NIC, storage, or accelerator cards are the conditions it plans for. Defenses route through PCIe Gen6 and Gen7 IDE with DMA isolation and MACsec, inline encryption with ECC and a TEE on the memory subsystem, and a ROM root of trust with a signed APU boot chain. Wow, this is PCIe Gen7?
For memory protection, AES-XTS and AES-GCM with rolling counters defend confidentiality and block replay attacks. DPA countermeasures frustrate side-channel extraction. The design keeps multi-tenant protection against malware even for authenticated code and encrypted data in use.
AMD is making its case for memory on package with density and reliability numbers. This integrated approach uses roughly 60 percent less area and reduces board size by around 2.5x, which is what allows it to fit PXI, 3U VPX, and PCIe form factors.
Secure memory on package shrinks the attack surface and keeps contents encrypted. On-package DRAM cuts latency, power, and footprint for SWaP-constrained designs, and always-on encryption protects data in use. AMD lists the operating temperature range as -40 to 100C for industrial, airborne, and outdoor use.
I miss the old Xilinx spec slides, but we are getting there with this one. Versal Premium Gen2 adds memory on package, PCIe Gen6 and CXL 3.1 with 128G transceivers that enable PCIe Gen7 and CXL 4.0, DDR5-6400 and LPDDR5X-8533 memory, enhanced security including PQC, MIPI C-PHY at 10 Gb/s and D-PHY at 4.5 Gbps, and improved DSP compute density.
AMD showcased the Versal Premium Gen2 adaptive SoC product line, featuring three SKUs. This 2VP3102 leads the family with 3.273M logic cells, 1.50M LUTs, and 7.6K DSP engines, while the 2VP3402 and 2VP3622 step down in logic capacity with the option for memory on package. These are 2024-2026 products that will be in the market for a long time.
Post-quantum crypto is not one size fits all for AMD. This crypto agility layer spans ML-KEM and HQC-KEM key encapsulation, ML-DSA and NTRU lattice-based signatures, plus LMS and XMSS options, with hybrid PQC plus ECC as an intermediate transition path. Global customers need PQC compliance across all regions. Xilinx had a large international market that quickly evaporated before the AMD acquisition, so that is one reason the FPGA side is very sensitive to regional flexibility.
AMD walked through a store-now, decrypt-later scenario for the quantum future. Data encrypted today is stored in the database, with server-side decryption deferred until a capable quantum computer arrives.
PCIe and CXL connectivity is provided via GTM2 transceivers and a configurable protocol module. This design supports PCIe Gen1 through Gen6 SerDes plus Gen7 direct to programmable logic at up to 64 GT/s, and CXL 4.0 direct to the PL at up to 128 GT/s.
AMD pairs the Versal Premium Gen2 with an EPYC processor to deliver host-to-accelerator performance. PCIe Gen6 and Gen7 carry acceleration, networking, and storage offload, while CXL provides coherent memory expansion that reduces stranded memory waste. PCIe IDE secures the host-to-accelerator path and keeps memory encrypted in flight.
A lot of folks have said “CXL is dead,” but companies like Marvell and Astera Labs we know are doing well there, and it looks like AMD is saying it can offer an FPGA to act as a controller.
Real-time information, compute, and decisions and reactions all work in concert, because physical AI never sleeps and must work all the time.
Versal Premium Gen2 carries 100G, 400G, and 600G multirate Ethernet cores, dual Arm Cortex-A72 application engines, dual real-time Cortex-R5F processors, a programmable-logic LDPC decoder and crypto engines, plus PCIe Gen6 with DMA and CXL 3.1.
Industrial and robotics use cases put Versal Premium Gen2 up against tight control loops alongside a Ryzen AI Embedded processor. Real-time input and analysis drive real-time action, with 10-microsecond loops and 10-40 ms reaction windows across the real-time I/O and RTOS path.
Remote medical diagnostic imaging needs secure communication, reliable real-time transmission, and resolution, packaged for a clinical setting.
AMD closed with its system differentiator. Co-design of the trust anchor, secure memory and data in motion, and high-speed interconnect for sensors and communication are the pillars that separate Versal Premium Gen2.
I wanted a bit more depth on this one, but it seems we are getting a lot of use cases rather than specs. This is a bit different than older Xilinx presentations.
Final Words
Versal Premium Gen2 matters because AMD is positioning one adaptive SoC family across physical AI, data center, and mission-critical systems while pushing security and memory onto the package. This EPYC pairing and CXL story give the platform an x86 path that competing adaptive parts lack. I have to say, the more that we use AI models for programming, the possibility to use FPGAs by a larger audience feels like it should be a key message in these kinds of presentations.
